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US 12,726,212 B2Granted
DTC linearization via mismatch-noise cancellation for digital fractional-N PLLs
AssigneeThe Regents of the University of California
InventorsIan Andrew Galton, Amr Eissa, Eslam Helal
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Abstract
A fractional-N PLL includes a reference oscillator, a multi-modulus divider-based phase-error-to-digital converter driven by the reference oscillator, a digital loop filter, and a digitally controlled oscillator. Digital-to-time to converter mismatch noise cancellation digital logic is between the phase-error-to-digital converter and the digital loop filter. Error from digital-to-time converter component mismatches is partially cancelled by the digital logic.
Claims9
A fractional-N PLL, comprising:
- a reference oscillator;
- a multi-modulus divider (MMD) based phase-error-to-digital converter (PEDC) driven by the reference oscillator;
- a digital loop filter;
- a digitally controlled oscillator;
- and
- digital-to-time to converter mismatch noise cancellation (DTC-MNC) digital logic between the PEDC and the digital loop filter;
- wherein error from digital-to-time converter component mismatches is partially cancelled by the DTC-MNC digital logic.
4 more elements
A fractional-N PLL, comprising:
- a reference oscillator;
- a multi-modulus divider (MMD) based phase-error-to-digital converter (PEDC) driven by the reference oscillator;
- a digital loop filter;
- a digitally controlled oscillator;
- and
- digital-to-time to converter mismatch noise cancellation (DTC-MNC) means between the PEDC and the digital loop filter for partially cancelling error from digital-to-time converter component mismatches.
3 more elements
Dependencies are inferred from the claim text.