Gain calibration of digital-to-time converter (DTC) used in fractional frequency dividers

A method performed in an open-loop modulator (OLM) circuit for generating a fractional output clock having a frequency which is a desired fraction of that of a reference clock, wherein said desired fraction comprises an integer component and a fractional component, said method comprising:

• generating, by delta-sigma modulation technique, a first sequence of codes from said integer component, and a corresponding second sequence of codes from said fractional component;
• dividing said reference clock based on each code of said first sequence of codes to form a divided signal, said divided signal having a period that is a multiple of the period of said reference clock, wherein the multiple is said each code;
• delaying, by a digital to time converter (DTC), in a first time interval, edges of interest of said divided signal, based on corresponding ones of a sequence of uncalibrated codes to generate said fractional output clock, said DTC providing a gain in generating said fractional output clock and said DTC having a gain-error;
• generating a feedback clock locked in phase to said fractional output clock;
• identifying a sequence of phase errors between said fractional output clock and said feedback clock, said sequence of phase errors indicative of said gain-error;
• transforming said second sequence of codes into a corresponding sequence of matched codes by high-pass filtering said second sequence of codes;
• generating a gain-adjustment-factor, by:
• multiplying each phase error of said sequence of phase errors with a corresponding one of said sequence of matched codes;
• low-pass filtering and scaling the result of said multiplying;
• and
• offsetting the scaled output by a fixed offset value;
• and
• multiplying each code of said second sequence of codes with said gain-adjustment-factor to generate a corresponding adjusted code of a sequence of adjusted codes;
• wherein said gain-adjustment-factor converges to a value equaling an inverse of a magnitude of said gain provided by said DTC at the end of said first time interval,
• wherein, starting from a second time interval following said first time interval, each edge of interest is delayed by said DTC by a time duration indicated by a corresponding adjusted code of said sequence of adjusted codes to generate said fractional output clock.

A system comprising:

• a line card coupled to receive a data packet, said line card to re-time said data packet with reference to a selected clock, and to transmit a re-timed packet;
• a first timing card to generate a first clock;
• and
• a power supply,
• wherein said line card comprises:
• a phase-locked loop (PLL) coupled to receive said first clock, said PLL to generate a reference clock locked to said first clock;
• and
• an open-loop-modulator (OLM) coupled to receive said reference clock and to generate a fractional output clock having a frequency which is a desired fraction of that of said reference clock, wherein said OLM comprises:
• a delta-sigma modulator (DSM) comprising:
• a first portion coupled to receive said integer component and to generate a first sequence of codes;
• and
• a second portion coupled to receive said fractional component and to generate a corresponding second sequence of codes, wherein said first sequence of codes comprises a set of a lower value and a set of a higher value together representing said desired fraction on average;
• a first divider coupled to receive said reference clock and each code of said first sequence of codes, and to generate a first divided signal having a period that is a multiple of the period of said reference clock, wherein the multiple is said each code;
• a first digital-to-time converter (DTC) coupled to generate said fractional output clock from said first divided signal, said DTC providing a gain and said DTC having a gain-error;
• and
• a DTC-gain calibration circuit to generate a sequence of adjusted codes, said DTC-gain calibration circuit comprising:
• a calibration phase-locked loop (PLL) coupled to receive said fractional output clock as a reference clock and to generate a feedback clock, said calibration PLL to synchronize said feedback clock with said reference clock, said calibration PLL having a forward path and a feedback path,
• a phase detector coupled to receive said fractional output clock and said feedback clock, and to generate a sequence of error signals representing phase error between said fractional output clock and said feedback clock at corresponding time points, said sequence of error signals indicative of said gain-error;
• a matching block coupled to receive said second sequence of codes and to generate a corresponding sequence of matched codes;
• and
• a first multiplier coupled to receive said sequence of matched codes and said sequence of error signals, and to generate a product of corresponding ones of said sequence of matched codes and said sequence of error signals as a sequence of first-multiplier outputs;
• a gain-adjustment-factor generator coupled to receive said sequence of first-multiplier outputs, and to generate a gain-adjustment-factor, said gain-adjustment-factor representing an inverse of a magnitude of said gain provided by said DTC;
• and
• a second multiplier coupled to receive said gain-adjustment-factor and to multiply each code of said second sequence of codes with said gain-adjustment-factor to generate said sequence of adjusted codes,
• wherein said first DTC operates to delay an edge of interest of said first divided signal by a time duration indicated by said corresponding adjusted code of said sequence of adjusted codes,
• wherein the signal transfer function of the combination of said second portion of said DSM and said matching block is matched with the signal transfer function of the combination of said calibration PLL and said phase detector.