Reducing non-linearity in a digital-to-time converter (DTC) when an input clock changes between lower and higher periods

A digital-to-time converter (DTC) for generating a fractional output clock from a divided signal based on a sequence of delay-codes, said DTC comprising:

• an input buffer, powered by a power supply, coupled to receive said divided signal and to generate an intermediate output, wherein said divided signal has a lower period and a higher period,
• wherein the current drawn from said power supply comprises a first average current magnitude when the period of said first divided signal equals said lower period, and a second average current magnitude when the period of said divided signal equals said higher period;
• a delay generator coupled to receive said intermediate output and to delay a corresponding edge of said intermediate output according to each delay-code of said sequence of delay-codes to generate said fractional output clock;
• and
• a correction-component, coupled to draw current from said power supply, to compensate for the difference between said first average current magnitude and said second average current magnitude to improve linearity of said DTC.

A system comprising:

• a line card coupled to receive a data packet, said line card to re-time said data packet with
• reference to a selected clock, and to transmit a re-timed packet;
• a first timing card to generate a first clock;
• and
• a power supply,
• wherein said line card comprises:
• a phase-locked loop (PLL) coupled to receive said first clock, said PLL to generate a reference clock locked to said first clock;
• and
• an open-loop-modulator (OLM) coupled to receive said reference clock and to generate a fractional output clock having a frequency which is a desired fraction of that of said reference clock, wherein said OLM comprises:
• a delta-sigma modulator (DSM) coupled to receive said desired fraction and to generate a sequence of first codes and a corresponding sequence of second codes, wherein said sequence of first codes comprises a set of a lower value and a set of a higher value together representing said desired fraction on average;
• a first divider coupled to receive said reference clock and each first code of said sequence of first codes, and to generate a divided signal having a period that is a multiple of the period of said reference clock, wherein the multiple is said each first code, such that said divided signal has different periods corresponding to said lower value and said higher value;
• a digital-to-time converter (DTC) coupled to generate said fractional output clock from said divided signal, wherein said DTC comprises:
• an input buffer, powered by said power supply, coupled to receive said divided signal and to generate an intermediate output,
• wherein the current drawn from said power supply comprises a first average current magnitude when said first code comprises said lower value, and a second average current magnitude when said first code comprises a higher value;
• a delay generator coupled to receive said intermediate output and to delay said intermediate output according to corresponding second code of said sequence of second codes to generate said fractional output clock;
• and
• a correction-component, coupled to draw current from said power supply, to compensate for the difference between said first average current magnitude and said second average current magnitude to improve linearity of said DTC.