Serializer and method for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHAN-TZUNG KE
Life of this patent
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Abstract
The present disclosure provides a circuit, which includes a clock generator, a selection control circuit, and a selection circuit. The clock generator is configured to divide an input clock signal into a first divided clock set and a second divided clock set, and generate a control clock set from the first divided clock set and the second divided clock. The selection control circuit is configured to generate a first selection signal and a second selection signal using the control clock set. The selection circuit is configured to sequentially output each bit of an input data signal within a duration of predetermined clock cycles of the input clock signal based on the first selection signal and the second selection signal.
Claims20
A circuit, comprising:
- a clock generator, configured to divide an input clock signal into a first divided clock set and a second divided clock set, and generate a control clock set from the first divided clock set and the second divided clock;
- a selection control circuit, configured to generate a first selection signal and a second selection signal based on the control clock set;
- and
- a selection circuit, configured to sequentially output each bit of an input data signal based on the first selection signal and the second selection signal.
A circuit, comprising:
- a clock generator, comprising:
- a first clock divider, configured to divide an input clock signal into a first divided clock set;
- and
- a second clock divider, configured to divide the input clock signal into a second divided clock set;
- wherein the first divided clock set and the second divided clock set comprise a plurality of first divided clock signals and a plurality of second divided clock signals generated by dividing the input clock signal in different powers of 2;
- a selection control circuit, configured to generate a first selection signal and a second selection signal based on a control clock set;
- and
- a selection circuit, configured to sequentially output each bit of an input data signal based on the first selection signal and the second selection signal.
A method for operating a serializer, the method comprising:
- dividing an input clock signal into a first divided clock set and a second divided clock set;
- in response to the serializer operating a non-2N-to-1 serialization mode, selecting the first divided clock set or the second divided clock set as a control clock set based on a selection control signal, wherein N is a positive integer;
- generating a first selection signal and a second selection signal based on one or more divided clock signals within the control clock set;
- and
- sequentially outputting each valid bit within an input data signal based on the first selection signal and the second selection signal.
Dependencies are inferred from the claim text.