Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link

A transmitter for use in data transmission over a serial link, wherein the link is configured to transmit digital video data and has at least one other characteristic of a transition minimized differential signaling link, said transmitter including:

• a video input for receiving video data;
• an auxiliary data input for receiving auxiliary data;
• outputs configured to be coupled to channels of the link, including a first output configured to be coupled to a clock channel of the link;
• and
• circuitry, coupled to the video input, the auxiliary data input, and at least some of the outputs including the first output, configured to assert output signals indicative of the auxiliary data and the video data to the outputs, and configured to assert a clock signal to the first output, wherein the clock signal is indicative of a video clock and at least one auxiliary clock for the auxiliary data.

A communication system, including:

• a receiver;
• a transmitter;
• and
• a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over a first channel of the link and at least one of the transmitter and the receiver is configured to transmit a binary signal to the other of the transmitter and the receiver over a second channel of the link, wherein the binary signal has periodic features that determine a pixel clock for the video data, and the binary signal determines a stream of data structures indicative of at least one stream of audio data and at least one additional clock for the at least one audio data stream.

A communication system, including:

• a receiver;
• a transmitter;
• and
• a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over a first channel of the link and at least one of the transmitter and the receiver is configured to transmit a binary signal to the other of the transmitter and the receiver over a second channel of the link, wherein the binary signal has periodic features that determine a pixel clock for the video data, and the binary signal determines a stream of data structures indicative of at least two streams of auxiliary data, wherein the stream of data structures is also indicative of at least two additional clocks, and each of the additional clocks is for a different stream of auxiliary data.

A communication system, including:

• a receiver;
• a transmitter;
• and
• a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data to the receiver over a first channel of the link and to transmit a binary signal to the receiver over a second channel of the link, wherein the binary signal has periodically occurring edges of a first type, the periodically occurring edges determine a video clock, the binary signal has edges of a second type, and relative timing between the edges of the second type and the edges of the first type is indicative of at least one of a stream of audio data, a clock for a stream of audio data, and a clock for each of at least two streams of auxiliary data, wherein the relative timing between the edges of the second type and the edges of the first type is indicative of a clock for a stream of audio data.

A receiver for coupling to a serial link, for use in a system including the link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

• a frequency synthesizer to generate, from a recovered version of the video clock, an auxiliary clock for the auxiliary data, wherein the auxiliary clock has a time-averaged frequency fau, wherein the frequency synthesizer includes a phase locked loop, and the phase locked loop includes:
• a voltage controlled oscillator having an output at which the auxiliary clock is asserted;
• and
• a dual-modulus frequency divider coupled to receive the auxiliary clock and configured to divide the frequency of the auxiliary clock by a selectable value L to generate a second clock, where L is a selected one of a first integer N and a second integer P, and the second clock has frequency f/M′, where M′ is a number, wherein the dual-modulus frequency divider is configured to operate cyclically to divide the frequency of the auxiliary clock by the first integer N and then by the second integer P, with a duty cycle that is controlled so that the time-averaged frequency of the second clock is equal to (Q/M)f, where Q has a predetermined value greater than N and less than P.

A receiver for coupling to a serial link, for use in a system including the link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

• a frequency synthesizer to generate, from a recovered version of the video clock, an auxiliary clock for the auxiliary data, wherein the auxiliary clock has a time-averaged frequency fau;
• and
• a second frequency divider coupled and configured to receive the recovered version of the video clock and to output a third clock having frequency f/M in response to the recovered version of the video clock, where M is an integer, and wherein the frequency synthesizer includes a phase locked loop, and the phase locked loop includes:
• a voltage controlled oscillator having an output at which the auxiliary clock is asserted;
• and
• a dual-modulus frequency divider coupled to receive the auxiliary clock and configured to divide the frequency of the auxiliary clock by a selectable value L to generate a second clock, where L is a selected one of a first integer N and a second integer P, and the second clock has frequency f/M′, where M′ is a number;
• a phase detector, coupled to receive the second clock and the third clock, and configured to generate a phase signal indicative of relative phase of the second clock and the third clock in response to said second clock and said third clock;
• and
• a loop filter coupled to receive the phase signal and configured to generate an error signal in response to the phase signal, wherein the voltage controlled oscillator is coupled to receive the error signal and configured to generate the auxiliary clock in response to said error signal.

A receiver for use in a system including a serial link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

• a frequency synthesizer configured to generate, from a recovered version of the video clock, an auxiliary clock for the auxiliary data, wherein the auxiliary clock has a time-averaged frequency fau, and the frequency synthesizer includes:
• a dual-modulus frequency divider coupled and configured to receive the recovered video clock and to divide the frequency of the recovered video clock by a selectable value Q to generate a first clock, where Q is a selected one of a first integer R and a second integer S;
• a phase detector, coupled to receive the first clock and a second clock, and configured to generate a phase signal indicative of relative phase of the first clock and the second clock in response to said first clock and said second clock;
• a loop filter coupled to receive the phase signal and configured to generate an error signal in response to the phase signal;
• a voltage controlled oscillator, coupled to receive the error signal, and configured to generate the auxiliary clock in response to said error signal;
• and
• a second dual-modulus frequency divider coupled to receive the auxiliary clock and configured to divide the frequency of the auxiliary clock by a second selectable value L to generate the second clock, where L is a selected one of a third integer N and a fourth integer P.

A receiver for use in a system including a serial link and a transmitter configured to transmit auxiliary data and a video clock to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and the video clock has frequency f, said receiver including:

• circuitry for generating a set of L recovered clocks, wherein each of the recovered clocks has the frequency f, is a recovered version of the video clock, and has a different phase φ=φ0+2π(m/L), where m is a non-negative integer in the range {0, . . . , L−1};
• a multiplexer and a preload counter coupled to the multiplexer, wherein each of the multiplexer and the preload counter is coupled to receive any selected one of the recovered clocks, and the multiplexer is configured to output a first clock having frequency (1±k/ML)f in response to said selected one of the recovered clocks, where k and M are integers;
• and
• a dual-modulus frequency divider coupled to receive the first clock and configured to divide the frequency of the first clock by a selectable value L to generate an auxiliary clock for the auxiliary data, where L is a selected one of a first integer N and a second integer P.

A communication system, including:

• a receiver;
• a transmitter;
• and
• a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the video data are transmitted at a video data rate, and packets of the auxiliary data are transmitted at an auxiliary data rate, and wherein the receiver comprises:
• rate determination circuitry coupled to receive time stamp data transmitted to the receiver over the link and configured to generate a rate signal indicative of the auxiliary data rate in response to the time stamp data, wherein the time stamp data are indicative of times at which the packets of the auxiliary data were transmitted by the transmitter;
• and
• auxiliary clock generation circuitry coupled and configured to receive the rate signal and to generate an auxiliary clock having frequency closely matching the auxiliary data rate in response to the rate signal.

A receiver for use in a system including a serial link and a transmitter configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, the video data are transmitted at a video data rate, and the auxiliary data are transmitted at an auxiliary data rate, said receiver including auxiliary clock generation circuitry for generating an auxiliary clock whose frequency closely matches the auxiliary data rate, said auxiliary clock generation circuitry including:

• FIFO circuitry including a FIFO memory, wherein the FIFO circuitry is coupled and configured to queue in the FIFO memory packets of the auxiliary data that have been transmitted to the receiver over the link, and to clock the packets out of the FIFO memory at a clock frequency determined by varying a reference frequency in response to a feedback signal, wherein at any instant during operation of said FIFO circuitry the FIFO memory is filled up to a FIFO level with a number of said packets;
• and
• feedback circuitry coupled to the FIFO circuitry and configured to generate the feedback signal, wherein said feedback signal is indicative of at least one of the FIFO level and a rate of change of the FIFO level.

A receiver for use in a system including a serial link and a transmitter configured to transmit data to the receiver over one or more channels of the link, said data including video data and auxiliary data, wherein the link is configured to transmit digital video data from the transmitter to the receiver and has at least one other characteristic of a transition minimized differential signaling link, and at least some of said data are transmitted at a data rate determined by a transmitter clock frequency, wherein the receiver includes clock generation circuitry for generating an auxiliary data clock for use in receiving the auxiliary data, wherein the auxiliary data clock has a receiver clock frequency, and wherein the auxiliary clock generation circuitry includes:

• circuitry for generating a binary value indicative of a ratio B/A, where A is an integer indicative of the transmitter clock frequency and B is an integer indicative of the receiver clock frequency, said circuitry comprising:
• a first counter configured to count repeatedly up to a value equal to 2m and then to reset, in response to a clock having the transmitter clock frequency, where m is an integer;
• and
• a second counter coupled to the first counter and configured to generate a second count value in response to a clock having the receiver clock frequency and to reset when the first counter resets, whereby each maximum value of the second count value is indicative of said ratio B/A.

A communication system, including:

• a receiver;
• a transmitter;
• and
• a communication link between the transmitter and the receiver, wherein the link is a serial link configured to transmit digital video data from the transmitter to the receiver and having at least one other characteristic of a transition minimized differential signaling link, the transmitter is configured to transmit video data and auxiliary data to the receiver over one or more channels of the link, wherein the video data are transmitted at a video data rate and packets of the auxiliary data are transmitted at an auxiliary data rate, wherein the receiver comprises auxiliary clock generation circuitry configured to generate an auxiliary clock having frequency closely matching the auxiliary data rate, and wherein the receiver is configured to transmit the auxiliary clock to the transmitter over a back channel of the link.