H03K 5/15026
With asynchronously driven series connected output stages
Official title: {with asynchronously driven series connected output stages}
H03K5/15026 (With asynchronously driven series connected output stages) appears on 199 US grants and 129 published applications in this corpus.
Search patents in H03K- Granted patents
- 199
- Published applications
- 129
- Assignees
- 128
- Inventors
- 392
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 3 | 0 |
| 1992 | 6 | 0 |
| 1993 | 4 | 0 |
| 1994 | 7 | 0 |
| 1995 | 4 | 0 |
| 1996 | 12 | 0 |
| 1997 | 6 | 0 |
| 1998 | 4 | 0 |
| 1999 | 4 | 0 |
| 2000 | 1 | 0 |
| 2001 | 2 | 2 |
| 2002 | 4 | 1 |
| 2003 | 2 | 5 |
| 2004 | 5 | 8 |
| 2005 | 5 | 6 |
| 2006 | 4 | 8 |
| 2007 | 4 | 8 |
| 2008 | 7 | 2 |
| 2009 | 3 | 14 |
| 2010 | 10 | 10 |
| 2011 | 11 | 5 |
| 2012 | 6 | 1 |
| 2013 | 5 | 1 |
| 2014 | 4 | 6 |
| 2015 | 6 | 0 |
| 2016 | 1 | 3 |
| 2017 | 10 | 8 |
| 2018 | 2 | 8 |
| 2019 | 11 | 4 |
| 2020 | 8 | 4 |
| 2021 | 6 | 8 |
| 2022 | 8 | 4 |
| 2023 | 5 | 3 |
| 2024 | 2 | 5 |
| 2025 | 5 | 3 |
| 2026 | 2 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Apparatus and method for generating circuit clock signal16 Jun 2026US 12,658,897 B2Beijing Youzhuju Network Technology Co., Ltd.
- Circuitry and a method for generating a set of output clock signals12 May 2026US 12,627,298 B2Imec Vzw
- Method for performing a charge-sharing operation and a charge pump circuit therefor13 May 2025US 12,301,109 B2Samsung Electronics Co., Ltd.
- Synchronizing devices using clock signal delay comparison15 Apr 2025US 12,278,887 B2Imagination Technologies Limited
- Low-power inter-die communication using delay lines1 Apr 2025US 12,267,075 B2QUALCOMM Incorporated
- Processing chip, design method, and electronic device19 Mar 2026US 2026/0081606 A1Huawei Technologies Co., Ltd.
- Topological structure for ip core, and ip core19 Feb 2026US 2026/0052769 A1
- Synchronising Devices Using Clock Signal Delay Comparison15 May 2025US 2025/0158798 A1Imagination Technologies Limited
- Semiconductor device including i/o system, and method of operating the same8 May 2025US 2025/0150076 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Four-phase clock buffer of twenty-five percent duty cycle27 Feb 2025US 2025/0070762 A1Realtek Semiconductor Corp.
Most cited
By later US patents
- Method and apparatus for clock distribution and for distributed clock synchronization189US 5,361,277 AAlberta Telecommunications Research Centre · 1994
- Clock signal latency elimination network104US 5,272,729 AInternational Business Machines Corporation · 1993
- Phase-locked delay loop for clock correction95US 5,646,564 AXilinx, Inc. · 1997
- Signal delay apparatus employing a phase locked loop81US 5,179,303 ANorthern Telecom Limited · 1993
- Clock multiplication circuit and method73US 5,359,232 ACyrix Corporation · 1994