Method for performing a charge-sharing operation and a charge pump circuit therefor

A charge pump circuit with a six-phase clock, comprising:

• a six-phase clock circuit;
• and
• a gate boosting charge pump configured to receive a plurality of clock signals from the six-phase clock circuit, wherein
• the six-phase clock circuit includes:
• a first Boolean logic circuit including a first delay circuit configured to output a first clock signal and a second delay circuit configured to output a second clock signal,
• a second Boolean logic circuit including a third delay circuit configured to output a third clock signal and a fourth delay circuit configured to output a fourth clock signal, and
• a tri-state buffer circuit configured to output a fifth clock signal and a sixth clock signal;
• and
• the gate boosting charge pump includes:
• a plurality of NMOS transistors configured to receive the first and third clock signals, wherein a first NMOS transistor of the plurality of NMOS transistors is configured to receive the first clock signal,
• a plurality of PMOS transistors configured to receive the second and fourth clock signals, wherein a first PMOS transistor of the plurality of PMOS transistors is configured to receive the fourth clock signal, and
• a plurality of pump capacitors, wherein each of the pump capacitors is configured to store an amount of charge,
• wherein the gate boosting charge pump is further configured to enable a charge-sharing operation to share the stored amount of charges between a plurality of parasitic capacitors,
• wherein the first and second Boolean logic circuit are configured to provide a dead time between each of the first, second, third, fourth, fifth and sixth clock signals,
• wherein the first Boolean logic circuit is configured to output a seventh clock signal and provide the seventh clock signal to the tri-state buffer circuit,
• wherein the second Boolean logic circuit is configured to output an eighth clock signal and provide the eighth clock signal to the tri-state buffer circuit, and
• the tri-state buffer circuit is configured to output the fifth and the sixth clock signals based on the seventh and eighth clock signals.