Low-power inter-die communication using delay lines

A system, comprising:

• a first die coupled to a serial communication link, a circuit on the first die including:
• a transmitter delay line including a first plurality of pulse generation circuits, each pulse generation circuit being configured to provide pulses in a corresponding one of N transmit enable signals, where Nis an integer greater than 1 and where each pulse generated by the first plurality of pulse generation circuits has a duration that is 1/Nth of a period of a transmit clock signal received at an input of the delay line;
• and
• a plurality of buffers coupled to a data source, each buffer being enabled by a corresponding transmit enable signal and configured to couple a signal representing an associated bit from the data source to a data line of the serial communication link while a pulse is present in the corresponding transmit enable signal;
• and
• a second die coupled to the serial communication link, a circuit on the second die including:
• one or more receiver delay lines, each receiver delay line including a second plurality of pulse generation circuits, each pulse generation circuit being configured to provide a pulse in a corresponding one of N control signals generated by the delay line from a bus clock signal received over a clock line of a serial communication link, wherein each pulse generated by the second plurality of pulse generation circuits has a duration that is 1/Nth of a period of the bus clock signal;
• and
• a plurality of latches coupled to the data line of a serial communication link, each latch being enabled using one control signal in the N control signals and being configured to capture state of the data line while a pulse is present in the one control signal.