Four-phase clock buffer of twenty-five percent duty cycle
AssigneeRealtek Semiconductor Corp.
InventorChia-Liang (Leon) Lin
Life of this patent
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Abstract
A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.
Claims12
A four-phase (hereafter 4-phase) clock buffer comprising:
- a first p-channel metal oxide semiconductor transistor (hereafter PMOST), a second PMOST, a third PMOST, and a fourth PMOST configured in a common-source ring topology to dispatch a first phase, a second phase, a third phase, and a fourth phase of a 4-phase output clock, respectively;
- and,
- a first n-channel metal oxide semiconductor transistor (hereafter NMOST), a second NMOST, a third NMOST, and a fourth NMOST configured in a common-source topology to control the first phase, the second phase, the third phase, and the fourth phase of the 4-phase output clock, in response to a first phase, a second phase, a third phase, and a fourth phase of a 4-phase input clock, respectively.
A four-phase (hereafter 4-phase) clock buffer comprising:
- a first n-channel metal oxide semiconductor transistor (hereafter NMOST), a second NMOST, a third NMOST, and a fourth NMOST configured in a common-source ring topology to dispatch a first phase, a second phase, a third phase, and a fourth phase of a 4-phase output clock, respectively;
- and,
- a first p-channel metal oxide semiconductor transistor (hereafter PMOST), a second PMOST, a third PMOST, and a fourth PMOST configured in a common-source topology to control the first phase, the second phase, the third phase, and the fourth phase of the 4-phase output clock, in response to a first phase, a second phase, a third phase, and a fourth phase of a 4-phase input clock, respectively.
A two-stage four-phase (hereafter 4-phase) clock buffer comprising a cascade of a first stage and a second stage, wherein:
- the first stage comprises four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock;
- and
- the second stage comprises four NMOSTs configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOSTs configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.
Dependencies are inferred from the claim text.