Phase-locked delay loop for clock correction

A phase-locked loop comprising:

• a phase detector including a first terminal connected to receive a reference input clock signal, and a second terminal connected to receive an output feedback signal, said phase detector producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said output feedback signal;
• a plurality of voltage controlled delay elements connected to receive said phase detector output signal, each of said voltage controlled delay elements having an input terminal and an output terminal and producing at said output terminal a signal that is delayed from a signal at said input terminal by an amount that is a function of said phase detector output signal;
• and
• means for placing into a delay path between said first and second terminals a selected number of said plurality of voltage controlled delay elements to produce said output feedback signal;
• said phase detector further comprising:
• a phase detector circuit providing an output signal indicating a phase mismatch between said reference input clock signal and said output feedback signal;
• an integrator for accumulating a charge indicative of said detected phase mismatch;
• and
• pass means connected to couple one of said reference input clock signal and said output feedback signal to said integrator when said phase detector circuit output signal indicates a phase mismatch;
• said phase detector further comprising:
• a range adjustment circuit comprising:
• an inverter connected to invert one of said reference input clock and output feedback signals;
• and
• a divide by N circuit for generating a range adjustment signal having a period that is a multiple of said reference input clock period;
• and
• means for activating said inverter and substituting said range adjustment signal for said reference input clock signal.

A phase-locked loop to compensate for propagation delays associated with distribution of an output clock signal, comprising:

• an input buffer connected to receive a reference input clock signal and to provide an output clock distribution signal corresponding thereto;
• a phase detector including a first terminal connected to receive said reference input clock signal from said input buffer, and a second terminal connected to receive a feedback signal, said phase detector producing an output signal indicative of a phase difference between said reference input clock signal and said feedback signal;
• a plurality of independently selectable voltage controlled delay elements connected to operate alone and in combination with one another, each voltage controlled delay element connected to receive said phase detector output signal, said voltage controlled delay elements producing said feedback signal, wherein said feedback signal is in-phase with said reference input clock signal, and is delayed by an integer number of clock cycles relative to said reference input clock signal;
• and
• selectable phase off-set means for producing any of a leading, lagging, and in-phase relationship between said reference input clock signal and said output clock distribution signal to compensate for propagation delays attendant with a selected output clock distribution scheme.

A method of compensating for propagation delays associated with distribution of an output clock signal, comprising the steps of:

• receiving a reference input clock signal at a first input terminal of a phase detector;
• receiving a feedback signal at a second input terminal of said phase detector;
• producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said feedback signal;
• generating a plurality of signal delays to be applied to said reference input clock signal, each of said signal delays being controlled by the voltage of said phase detector output signal;
• selectively applying any combination of said plurality of signal delays to said reference input clock signal to produce said feedback signal such that said feedback signal is brought into phase with said reference input clock signal;
• producing said output clock signal having a selected one of a leading, lagging, and in-phase relationship to said feedback signal to compensate for propagation delays attendant with distribution of said output clock signal.

A method of compensating for propagation delays associated with distribution of an output clock signal, comprising the steps of:

• receiving a reference input clock signal at a first input terminal of a phase detector;
• receiving a feedback signal at a second input terminal of said phase detector;
• producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said feedback signal;
• generating a plurality of signal delays to be applied to said reference input clock signal, each of said signal delays being controlled by the voltage of said phase detector output signal;
• selectively combining said plurality of signal delays to produce said feedback signal such that said feedback signal is brought into phase with said reference input clock signal;
• producing said output clock signal having a selected one of a leading, lagging, and in-phase relationship to said feedback signal to compensate for propagation delays attendant with distribution of said output clock signal;
• and
• further comprising the steps of:
• detecting a phase mismatch between said reference input clock signal and said feedback signal;
• and
• accumulating a charge indicative of said detected phase mismatch in an integrator when a phase mismatch is detected.

A method of compensating for propagation delays associated with distribution of an output clock signal, comprising the steps of:

• receiving a reference input clock signal at a first input terminal of a phase detector;
• receiving a feedback signal at a second input terminal of said phase detector;
• producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said feedback signal;
• generating a plurality of signal delays to be applied to said reference input clock signal, each of said signal delays being controlled by the voltage of said phase detector output signal;
• selectively combining said plurality of signal delays to produce said feedback signal such that said feedback signal is brought into phase with said reference input clock signal;
• producing said output clock signal having selected one of a leading, lagging, and in-phase relationship to said feedback signal to compensate for propagation delays attendant with distribution of said output clock signal;
• and
• further comprising range adjustment steps of:
• inverting one of said reference input clock and feedback signals;
• dividing by N said reference input clock signal to provide a temporary reference input signal having a period that is a multiple of said reference input clock period;
• and
• replacing said phase detector output signal with a temporary phase detector output signal indicative of a phase difference between said temporary reference input signal and a complement of said feedback signal.

A method of compensating for propagation delays associated with distribution of an output clock signal, comprising the steps of:

• receiving reference input clock signal at a first input terminal of a phase detector;
• receiving a feedback signal at a second input terminal of said phase detector;
• producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said feedback signal;
• generating a plurality of signal delays to be applied to said reference input clock signal, each of said signal delays being controlled by the voltage of said phase detector output signal;
• selectively combining said plurality of signal delays to produce said feedback signal such that said feedback signal is brought into phase with said reference input clock signal;
• producing said output clock signal having a selected one of a leading, lagging, and in-phase relationship to said feedback signal to compensate for propagation delays attendant with distribution of said output clock signal;
• and
• further comprising the steps of:
• receiving said reference input clock signal and said feedback signal;
• deriving a delayed reference input clock signal and a delayed feedback signal therefrom;
• and
• decoding a phase-lock status signal from said reference input clock signal, said feedback signal, and said delayed reference input clock and feedback signals, said status signal being indicative of a delay path locked and unlocked condition.

A method of compensating for propagation delays associated with distribution of an output clock signal, comprising the steps of:

• receiving a reference input clock signal at a first input terminal of a phase detector;
• receiving a feedback signal at a second input terminal of said phase detector;
• producing a phase detector output signal indicative of a phase difference between said reference input clock signal and said feedback signal;
• generating a plurality of signal delays to be applied to said reference input clock signal, each of said signal delays being controlled by the voltage of said phase detector output signal;
• selectively combining said plurality of signal delays to produce said feedback signal such that said feedback signal is brought into phase with said reference input clock signal;
• producing said output clock signal having a selected one of a leading, lagging, and in-phase relationship to said feedback signal to compensate for propagation delays attendant with distribution of said output clock signal;
• and
• further comprising the step of:
• selectively switching between a normal mode of operation when said reference input clock signal and said feedback signal are phase-locked;
• and a range adjustment mode of operation in which a range adjustment circuit is coupled to said reference input clock signal and said feedback signal when said reference input clock signal and said feedback signal are unlocked, wherein a range adjustment is made to bring said signal delays within their operating range.