Topological structure for ip core, and ip core

An IP core, comprising:

• a substrate, a drive chip provided on the substrate, a plurality of loads, and a connection structure between the plurality of loads and the drive chip;
• wherein a topological structure connected between the plurality of loads and the drive chip comprises a first topological structure and a second topological structure;
• wherein the first topological structure comprises the drive chip, multi-stage first signal lines and at least two first loads;
• a signal output of one first signal line of a previous stage is connected with a signal input of two parallel first signal lines of the next stage, and a signal input of a first signal line of a first stage is connected with a signal output of the drive signal;
• an output of each of the first signal lines of a last stage is connected with one first load;
• the second topological structure comprises a plurality of branch structures, each of the branch structures comprises at least one second load, and a signal input of each of the branch structures is connected with a signal output of one first signal line of a last stage of the first topological structure.