Clock multiplication circuit and method

A method of generating a clock signal with a frequency that is a multiplication of an input clock frequency, comprising the steps of:

• (a) detecting an active edge of the input clock;
• (b) responsive to the detection of an active edge of the input clock, generating a first output clock edge corresponding to the active edge, and then generating n more output clock edges (where n is at least two) by successively feeding back through a delay line the first output clock edge and the next n-1 output clock edges;
• and
• (c) inhibiting the generation of output clock edges after generation of the n output clock edges after the first output clock edge.

A clock multiplier circuit for generating an output clock signal with a frequency that is a multiplication of an input clock frequency, comprising:

• (a) detection means for detecting an active edge of the input clock;
• (b) edge generating means, including a delay line, responsive to the detection of an active edge of the input clock for generating a first output clock edge corresponding to the active edge, and then generating n more output clock edges (where n is at least two) by successively feeding back through the delay line the first output clock edge and the next n-1 output clock edges, thereby providing the output clock signal defined by the output clock edges;
• and
• (c) inhibiting means responsive to the generation of output clock edges for inhibiting the edge generating circuitry after generation of the n output clock edges after the first output clock edge.