Clock signal latency elimination network

A digital clock timing network for an integrated circuit chip having an internal clock circuit with a predetermined delay therethrough, said digital clock timing network receiving an input clock signal and generating therefrom a timing signal, said timing signal being passed through said chip's internal clock circuit to produce a chip clock signal, said chip clock signal being in phase with and offset from said input clock signal by at least one cycle, said digital clock timing network comprising:

• a delay circuit having an input coupled to receive said input clock signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a corresponding delay signal as said input clock signal propagates through said delay circuit;
• a plurality of pulse generators, each of said pulse generators being coupled to receive a respective one of said delay signals and output in response thereto a pulse signal, each of said pulse signals having a duration substantially less than the period of said input clock signal;
• and
• a control network coupled to receive as input said pulse signals output from said plurality of pulse generators, said control network generating a timing signal for output to said internal clock circuit, said timing signal having a period equal to a multiple of the period of said input clock signal minus an interval of time substantially equal to the predetermined delay through the internal clock circuit of said integrated circuit chip such that passing of said timing signal through said internal clock circuit produces a chip clock signal output substantially in phase with and offset by at least one cycle from said input clock signal.

An integrated semiconductor chip circuit for reducing clock latency resulting from passing an input clock signal through a predetermined internal clock circuit to produce a chip clock signal, said predetermined internal clock circuit including a receiver and clock powering logic, said integrated circuit comprising:

• a variable delay element connected between said receiver and said clock powering logic of said predetermined internal clock circuit, said variable delay element including a control input for receiving a select signal determinative of a delay therethrough, said variable delay element receiving at a first input said input clock signal after passing through said receiver of said predetermined internal clock circuit;
• a phase detector coupled to receive as inputs the input clock signal applied to the variable delay element and said chip clock signal being output from said clock powering logic, said phase detector outputting a phase difference signal representative of the difference in phase between said clock inputs;
• and
• control circuitry associated with the phase detector for receiving said phase difference signal and producing therefrom the select signal, said control circuitry including means for applying said select signal to the control input of said variable delay element, said select signal operating to select the clock delay through said variable delay element such that said chip clock signal output from said clock powering logic is substantially in phase with and offset from said input clock signal by at least one clock cycle.