G11C 7/1066
Output synchronization
Official title: {Output synchronization}
G11C7/1066 (Output synchronization) appears on 2,514 US grants and 2,427 published applications in this corpus.
Search patents in G11C- Granted patents
- 2,514
- Published applications
- 2,427
- Assignees
- 312
- Inventors
- 2,706
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 3 | 0 |
| 1998 | 5 | 0 |
| 1999 | 13 | 0 |
| 2000 | 33 | 0 |
| 2001 | 58 | 21 |
| 2002 | 72 | 86 |
| 2003 | 81 | 112 |
| 2004 | 102 | 108 |
| 2005 | 88 | 104 |
| 2006 | 92 | 123 |
| 2007 | 114 | 134 |
| 2008 | 119 | 107 |
| 2009 | 97 | 110 |
| 2010 | 99 | 100 |
| 2011 | 117 | 96 |
| 2012 | 86 | 73 |
| 2013 | 94 | 84 |
| 2014 | 100 | 72 |
| 2015 | 74 | 78 |
| 2016 | 96 | 59 |
| 2017 | 89 | 72 |
| 2018 | 68 | 80 |
| 2019 | 112 | 128 |
| 2020 | 129 | 107 |
| 2021 | 122 | 105 |
| 2022 | 87 | 101 |
| 2023 | 108 | 148 |
| 2024 | 111 | 99 |
| 2025 | 97 | 73 |
| 2026 | 41 | 47 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Signal retiming within memory systems22 Sep 2026US 12,744,065 B2Micron Technology, Inc.
- Memory controller communicating with vertically stacked dies and semiconductor device including the same8 Sep 2026US 12,731,622 B2Samsung Electronics Co., Ltd.
- Memory system25 Aug 2026US 12,717,690 B2SK hynix Inc.
- Memory system and memory chip25 Aug 2026US 12,717,732 B2Etron Technology, Inc.
- Apparatuses, systems, and methods for data timing alignment with fast alignment mode25 Aug 2026US 12,718,866 B2Micron Technology, Inc.
- Semiconductor system performing training operation1 Oct 2026US 2026/0301786 A1SK hynix Inc.
- Semiconductor device1 Oct 2026US 2026/0301827 A1Kioxia Corporation
- Semiconductor apparatus adjusting a phase skew between a clock signal and data24 Sep 2026US 2026/0290417 A1SK hynix Inc.
- Storage device and data training method thereof10 Sep 2026US 2026/0268951 A1Samsung Electronics Co., Ltd.
- Read operations for a memory array and register13 Aug 2026US 2026/0237411 A1Micron Technology, Inc.
Most cited
By later US patents
- Output enable signal generation circuit of semiconductor memory1,017US 8,400,851 B2SK hynix Inc. · 2013
- Apparatus for synchronously generating clock signals in a data processing system430US 5,243,703 ARambus Inc. · 1993
- Memory system having synchronous-link DRAM (SLDRAM) devices and controller383US 6,442,644 B1Advanced Memory International, Inc. · 2002
- Integrated circuit I/O using high performance bus interface325US 5,319,755 ARambus Inc. · 1994
- Memory circuitry having bus interface for receiving information in packets and access time registers282US 5,606,717 ARambus Inc. · 1997