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US 12,744,065 B2Granted
Signal retiming within memory systems
AssigneeMicron Technology, Inc.
InventorsGyan Prakash, Nidhir Kumar, Sandeep Dwivedi
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Abstract
A method includes training a timing flip-flop circuit positioned between a controller and a memory resource, providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals, serializing the plurality of output clock signals and the plurality of output data signals, and providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.
Claims16
A method comprising:
- training a timing flip-flop circuit positioned between a controller and a memory resource;
- providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals;
- serializing the plurality of output clock signals and the plurality of output data signals, wherein serializing the plurality of output clock signals and the plurality of output data signals further comprises decoupling a timing budget between the controller and the memory resource;
- and
- providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.
2 more elements
An apparatus, comprising:
- a controller;
- a plurality of memory dice;
- and
- a memory device interface to transfer communication between the controller and the plurality of memory dice, the memory device interface comprising:
- a first set of timing flip-flop circuits to receive a first set of signals from the controller;
- a first serializer to retime the first set of signals from the controller prior to providing the first set of signals to one or more memory dice of the plurality of memory dice;
- a second set of timing flip-flop circuits to receive a second set of signals from the plurality of memory dice;
- a second serializer to retime the second set of signals from the memory dice prior to providing the second set of signals to the controller;
- a delay-locked loop (DLL) component;
- and
- a duty cycle corrector (DCC) circuit.
8 more elements
A system comprising:
- a memory sub-system comprising a non-volatile memory device;
- and
- a processing device coupled to the memory sub-system by a memory device interface, the memory device interface comprising:
- a first set of timing flip-flop circuits to receive a first set of signals from the processing device and register a first value associated with the first set of signals;
- a first serializer to retime the first set of signals from the processing device based on the first value prior to providing the first set of signals to one or more memory dice of the non-volatile memory device;
- a second set of timing flip-flop circuits to receive a second set of signals from the non-volatile memory device and register a second value associated with the second set of signals;
- a second serializer to retime the second value from the non-volatile memory device based on the second value prior to providing the second set of signals to the processing device;
- and
- wherein the processing device is configured to perform:
- a first training operation between the processing device and the first set of timing flip-flop circuits,
- a second training operation between the first set of timing flip-flop circuits and the non-volatile memory device,
- a third training operation between the non-volatile memory device and the second set of timing flip-flop circuits, and
- a fourth training operation between the second set of timing flip-flop circuits and the processing device.
10 more elements
An apparatus, comprising:
- a controller;
- a plurality of memory dice;
- and
- a memory device interface to transfer communication between the controller and the plurality of memory dice, the memory device interface comprising:
- a first set of timing flip-flop circuits to receive a first set of signals from the controller;
- a first serializer to retime the first set of signals from the controller prior to providing the first set of signals to one or more memory dice of the plurality of memory dice;
- a second set of timing flip-flop circuits to receive a second set of signals from the plurality of memory dice;
- a second serializer to retime the second set of signals from the memory dice prior to providing the second set of signals to the controller, wherein the controller is configured to train the memory device interface through:
- a first write training operation between the controller and the first set of timing flip-flop circuits by sending a first write request to the first set of timing flip-flop circuits at a first frequency and determining an accuracy of the first write request at the first set of timing flip-flop circuits at a second frequency;
- and
- a second write training operation between the first set of timing flip-flop circuits and the plurality of memory dice.
8 more elements
Dependencies are inferred from the claim text.