Memory controller communicating with vertically stacked dies and semiconductor device including the same

A semiconductor device comprising:

• at least one first die including a memory cell array;
• and
• a second die configured to communicate with the first die via a plurality of through silicon vias (TSVs),
• wherein the second die comprises:
• a memory controller configured to control a memory operation on the first die;
• and
• a physical layer (PHY) region configured to:
• receive from the memory controller, as an input signal, a command/address including a plurality of bits in relation with a control of the memory operation;
• generate bits of the command/address having M phases based on first through Kth clock signals having different phases from each other as an output signal;
• and
• transmit the output signal to the first die via the TSVs (K is an integer of 2 or more, and M is an integer greater than K).

A memory controller comprising:

• a memory control unit configured to control a memory operation on a memory device;
• and
• a physical layer (PHY) region configured to communicate with the memory device via a plurality of through silicon vias (TSVs),
• wherein the PHY region comprises:
• a multi-phase clock generator configured to generate a first clock signal and a second clock signal having different phases from each other;
• and
• first through Mth TSV circuit blocks, each configured to receive at least one of first through Mth input signals from the memory control unit, and output, to the TSVs, at least one of first through Mth output signals having different phases from each other by processing the first through Mth input signals based on the first clock signal and the second clock signal (M is an integer of 3 or more),
• wherein the phases of the first through Mth output signals comprise phases corresponding to the first clock signal and the second clock signal, and phases of inverted clock signals that are an inverted form of the first clock signal and the second clock signal.