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US 2026/0301786 A1Published application
Semiconductor system performing training operation
AssigneeSK hynix Inc.
InventorsJoon Hong PARK, Sang Sic YOON
Life of this patent
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Abstract
A semiconductor system includes a controller and a memory device. The controller outputs first and second data during a write operation, receives the first and second data during a read operation, and tunes a delay quantity of output of the first and second data. The memory device stores the first data in a data storage circuit and the second data in a meta storage circuit during the write operation, and outputs, to the controller, the first and second data from the data storage circuit and the meta storage circuit during the read operation.
Claims25
A semiconductor system comprising:
- a controller configured to output first and second groups of data after a start of a write operation of a training operation, configured to receive the first and second groups of data after a start of a read operation of the training operation, and configured to tune a delay quantity by which the first and second groups of data are output;
- and
- a memory device configured to receive the first group of data through a first group of data transfer circuits that input and output data, store the first group of data in a data storage circuit, receive the second group of data through a second group of data transfer circuits that input and output error information, and store the second group of data in a meta storage circuit after the start of the write operation of the training operation and further configured to output the first group of data stored in the data storage circuit to the controller and output the second group of data stored in the meta storage circuit to the controller after the start of the read operation of the training operation.
A memory device comprising:
- a data input and output circuit configured to generate a first group of transfer data by receiving a first group of data, generate a second group of transfer data by receiving a second group of data after a start of a write operation of a training operation, and further configured to generate the first group of data by receiving the first group of transfer data generated from internal data and generate the second group of data by receiving the second group of transfer data, after the start of a read operation of the training operation;
- a data storage circuit comprising a plurality of banks configured to store the internal data generated from the first group of transfer data in a bank, which is selected from among the plurality of banks based on an address after the start of the write operation of the training operation and further configured to output the internal data stored in the selected bank after the start of the read operation of the training operation;
- and
- a meta storage circuit comprising a plurality of registers, configured to store the second group of data in a register, which is selected from among the plurality of registers based on the address after the start of the write operation of the training operation and further configured to output the second group of data stored in the selected register after the start of the read operation of the training operation.
1 more element
A memory device comprising:
- a first data transfer circuit configured to receive first data, store the first data in a write pipe circuit and a read pipe circuit after a start of a write operation of a training operation, and output the first data stored in the read pipe circuit after a start of a read operation of the training operation;
- a second data transfer circuit configured to generate transfer data by receiving second data after the start of the write operation of the training operation and further configured to generate the second data from test meta data and output the second data after the start of the read operation of the training operation;
- and
- a meta storage circuit comprising a plurality of registers, and configured to store the transfer data in a register, which is selected from among the plurality of registers based on an address after the start of the write operation of the training operation and configured to output the transfer data stored in the selected register as the test meta data after the start of the read operation of the training operation.
1 more element
Dependencies are inferred from the claim text.