G11C 5/146
Substrate bias generators
Official title: {Substrate bias generators (G11C5/141 takes precedence)}
G11C5/146 (Substrate bias generators) appears on 337 US grants and 191 published applications in this corpus.
Search patents in G11C- Granted patents
- 337
- Published applications
- 191
- Assignees
- 101
- Inventors
- 503
- Latest grant
- 21 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 0 | 0 |
| 1984 | 3 | 0 |
| 1985 | 3 | 0 |
| 1986 | 1 | 0 |
| 1987 | 3 | 0 |
| 1988 | 4 | 0 |
| 1989 | 1 | 0 |
| 1990 | 3 | 0 |
| 1991 | 3 | 0 |
| 1992 | 4 | 0 |
| 1993 | 5 | 0 |
| 1994 | 8 | 0 |
| 1995 | 8 | 0 |
| 1996 | 6 | 0 |
| 1997 | 13 | 0 |
| 1998 | 25 | 0 |
| 1999 | 21 | 0 |
| 2000 | 16 | 0 |
| 2001 | 20 | 5 |
| 2002 | 12 | 6 |
| 2003 | 9 | 12 |
| 2004 | 5 | 8 |
| 2005 | 6 | 7 |
| 2006 | 6 | 6 |
| 2007 | 6 | 5 |
| 2008 | 5 | 9 |
| 2009 | 4 | 5 |
| 2010 | 8 | 7 |
| 2011 | 7 | 3 |
| 2012 | 3 | 2 |
| 2013 | 3 | 4 |
| 2014 | 6 | 10 |
| 2015 | 9 | 10 |
| 2016 | 12 | 8 |
| 2017 | 13 | 13 |
| 2018 | 9 | 7 |
| 2019 | 10 | 11 |
| 2020 | 11 | 12 |
| 2021 | 11 | 7 |
| 2022 | 9 | 10 |
| 2023 | 10 | 7 |
| 2024 | 5 | 1 |
| 2025 | 4 | 4 |
| 2026 | 4 | 12 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Memory with bitcell-to-periphery interface tap cell21 Jul 2026US 12,690,183 B2QUALCOMM Incorporated
- Reduction in chip area through design-technology co-optimization31 Mar 2026US 12,592,264 B2SanDisk Technologies LLC
- Non-retention mode leakage reduction without impacting the cell content in the retention mode31 Mar 2026US 12,592,274 B1Synopsys, Inc.
- Systems and methods for dual standby modes in memory17 Mar 2026US 12,580,010 B2Everspin Technologies, Inc.
- Module25 Nov 2025US 12,482,732 B2Murata Manufacturing Co., Ltd.
- Sense amplifier and memory device including the same9 Jul 2026US 2026/0196263 A1Samsung Electronics Co., Ltd.
- Systems and methods for dual standby modes in memory2 Jul 2026US 2026/0188364 A1Everspin Technologies, Inc.
- Memory read out circuit18 Jun 2026US 2026/0171127 A1eMemory Technology Inc.
- Sense amplifier reducing capacitive coupling effect and a sense circuit and a memory device comprising the same18 Jun 2026US 2026/0171164 A1eMemory Technology Inc.
- Erasable programmable non-volatile memory cell18 Jun 2026US 2026/0173370 A1eMemory Technology Inc.
Most cited
By later US patents
- Semiconductor device316US 6,341,087 B12002
- Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device213US 5,646,900 AMitsubishi Denki Kabushiki Kaisha · 1997
- Pass gate circuit with body bias control190US 5,880,620 AXilinx, Inc. · 1999
- Semiconductor integrated circuit incorporated with substrate bias control circuit168US 5,461,338 ANEC Corporation · 1995
- Back biasing of FD-SOI circuit blocks162US 11,127,738 B2Xcelsis Corporation · 2021