Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device

A semiconductor memory device comprising:

• a first and second bit lines each connecting a predetermined number of memory cells;
• a sense amplifier including a first sense transistor coupled between a first node and said first bit line and having a control gate coupled to said second bit line and a first backgate, and a second sense transistor coupled between said first node and said second bit line and having a control gate coupled to said first bit line and a second backgate, said first and second backgates connected to a first backgate node, for differentially amplifying potentials on said first and second bit lines;
• a first sense enable transistor coupled between a first power node and said first node and responsive to a first sense amplifier enable signal being active for electrically connecting said first power node and said first node;
• precharge circuitry coupled to said first node for precharging said first node at an intermediate potential between a first power potential and a second power potential different from said first power potential in response to a precharge instructing signal being active;
• first backgate potential generator operating with said first and second power potentials for generating a first backgate precharge potential at a level between said intermediate potential and said second power potential;
• a first means coupled between said first backgate potential generator and said first backgate node for transmitting said first backgate precharge potential onto said first backgate node in response to a first control signal being active;
• a second means coupled between said first node and said first backgate node for electrically connecting said first node and said first backgate node in response to a second control signal being active;
• and
• controller coupled to receive a memory cycle start instructing signal and responsive to activation of said memory cycle start instructing signal for activating said first control signal for application to said first means prior to activation of said first sense amplifier enable signal, and for activating said second control signal during activation of said first sense amplifier enable signal, said precharge instructing signal being deactivated in response to activation of said memory cycle start instruct signal, and said first sense amplifier enable signal being activated in response to the activation of said memory cycle start instructing signal.