Erasable programmable non-volatile memory cell

An erasable programmable non-volatile memory cell, comprising:

• a first well region formed in a surface of a semiconductor substrate;
• a first gate structure and a second gate structure formed on the first well region, wherein the first gate structure is located beside a first side of the second gate structure, the first gate structure includes a first extension segment, and the first extension segment is located beside a second side of the second gate structure;
• a first spacer and a second spacer, wherein the first spacer is in contact with a sidewall of the first gate structure, and the second spacer is in contact with a sidewall of the second gate structure, wherein the first spacer and the second spacer are overlapped with each other in a region between the first gate structure and the second gate structure;
• a first lightly doped drain region formed in the first well region;
• a first merged doped region and a second merged doped region formed in the first well region, wherein the first merged doped region is located beside a first side of the first gate structure, the first lightly doped drain region is located beside a second side of the first gate structure and a first side of the second gate structure, and the second merged doped region is located beside a second side of the second gate structure;
• a metal layer formed over the second gate structure;
• a source line electrically connected with the first merged doped region;
• a word line electrically connected with the first gate structure;
• a bit line electrically connected with the second merged doped region;
• and
• an assist line electrically connected with the metal layer,
• wherein the second gate structure and the metal layer are collaboratively formed as a first plate capacitor, a first terminal of the first plate capacitor is electrically connected to the assist line, and a second terminal of the first plate capacitor is electrically connected to the second gate structure,
• wherein the first gate structure and the second gate structure are collaboratively formed as a second plate capacitor, a first terminal of the second plate capacitor is electrically connected to the word line, and a second terminal of the second plate capacitor is electrically connected to the second gate structure,
• wherein the first merged doped region, the first gate structure and the first lightly doped drain region are collaboratively formed as a select transistor, and the first lightly doped drain region, the second gate structure and the second merged doped region are collaboratively formed as a floating gate transistor.