Back biasing of FD-SOI circuit blocks

A microelectronic circuit structure comprising a stack of bonded layers including a bottom layer and at least one upper layer, the at least one upper layer comprising an oxide layer having a back surface and a front surface closer to said bottom layer than said back surface, a plurality of fully depleted silicon-on-insulator (FD-SOI) transistors built on the front surface of the oxide layer;

• and at least a first back gate line and a second separate back gate line in direct contact with and extending above the back surface of the oxide layer for independently providing a first back gate bias to a first group of said plurality of transistors and a second back gate bias to a second different group of said plurality of transistors and maintaining a third group of said plurality of transistors free from electrical communication with the first and second back gate lines and other back gate lines, wherein a first circuit block comprises said first group of said plurality of transistors and a second circuit block comprises said second group of said plurality of transistors, wherein the first and the second circuit blocks are different types of functional circuit blocks configured to receive the independent first and second back gate bias respectively, wherein an end of the first back gate line extends on the oxide layer and vertically overlaps a region defined between the first and the second groups of the transistors,
• wherein said at least one upper layer comprises a first upper layer and a second upper layer, wherein the second upper layer is bonded to the first upper layer through direct bonding interconnect (DBI), and
• wherein first back gate lines for providing said first back gate bias to respective transistors of the first and second upper layers in said first group are connected to each other.