Memory with bitcell-to-periphery interface tap cell
AssigneeQUALCOMM Incorporated
InventorsChannappa Desai, Sunil Sharma, Anne Srikanth, Sherin Bose, Pradeep Jayadev Kodlipet, Biju Manakkam Veetil, Rahul Biradar, Sung Son, Manjeet Singh Lowanshi, Kamlesh Kumar
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Abstract
A memory includes a periphery separated from one or more banks by a bitcell-to-periphery interface. The periphery includes logic circuits for the reading and writing to bitcells within the neighboring banks. Tap cells for the biasing of the periphery extend across the bitcell-to-periphery interface.
Claims17
A memory integrated onto a substrate, the substrate being doped according to a first conductivity type, the memory comprising:
- a first bank of bitcells;
- a periphery for the first bank of bitcells;
- a first bitcell-to-periphery interface having a first boundary shared with the first bank of bitcells and having a second boundary shared with the periphery, wherein the substrate includes a first well doped according to a second conductivity type that extends across the periphery;
- and
- a first tap cell doped according to the second conductivity type for biasing the first well, the first tap cell being located in a portion of the first well within the first bitcell-to-periphery interface,
- wherein the first conductivity type is p-type and the second conductivity type is n-type, the first well being a first n-well and the first tap cell being a first n-doped tap cell,
- wherein the first n-well has a height of two standard cells, and
- wherein the first n-doped tap cell has a height of a single standard cell.
A method of biasing a periphery of a memory, comprising:
- biasing a first n-well portion of the periphery from a first n-doped tap cell in a first interface between the periphery and a first bank of bitcells;
- biasing a first p-doped substrate portion of the periphery from a first p-doped tap cell in the first interface;
- and
- biasing a second n-well portion of the periphery from a second n-doped tap cell in the first interface, wherein the first p-doped substrate portion of the periphery separates the first n-well portion from the second n-well portion.
A memory, comprising:
- a first bank of bitcells;
- a second bank of bitcells;
- a periphery for the first bank of bitcells and for the second bank of bitcells;
- a first interface between the first bank of bitcells and the periphery;
- a second interface between the second bank of bitcells and the periphery;
- and
- a plurality of n-doped tap cells for biasing n-well portion of the periphery, the plurality of n-doped tap cells being located within at least one of the first interface and the second interface.
Dependencies are inferred from the claim text.