Non-retention mode leakage reduction without impacting the cell content in the retention mode

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• generate a circuit design that comprises bias circuitry that controls a supply voltage of a load, the bias circuitry comprising:
• a first power gate circuit comprising a first transistor and a second transistor connected in series,
• wherein the bias circuitry controls the first transistor independent of the second transistor;
• and
• wherein a gate of the second transistor is coupled to a shutdown control signal that turns OFF the second transistor during a shutdown mode and turns ON the second transistor during an operating mode.

A method, comprising:

• activating first and second controls to turn ON respective first and second series-connected transistors of a first power gate circuit to set a supply voltage of a load to a first voltage in an operating mode, wherein a threshold voltage of the first transistor is less than a threshold voltage of the second transistor;
• activating a third control to turn ON a third transistor to diode-connect the first transistor to reduce the operating voltage to a second voltage in a reduced power consumption mode;
• and
• deactivating the first, second, and third controls to turn OFF the first, second, and third transistors, respectively, to reduce the operating voltage to zero volts in a shutdown mode.