Sense amplifier and memory device including the same
AssigneesSamsung Electronics Co., Ltd., UIF (University Industry Foundation), Yonsei University
InventorsHyunjun KIM, Seong-ook JUNG, Wonhyeok HONG, Giseok KIM
Life of this patent
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Abstract
The sense amplifier includes a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and an input node, a second NMOS transistor connected between the input node and a ground, a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series between the power supply voltage and the ground, a first switch connected between a first node between the first PMOS transistor and the first NMOS transistor and a second node between the second PMOS transistor and the third NMOS transistor, and a second switch connected between the second node and an output node.
Claims20
A sense amplifier comprising:
- a first p-channel metal–oxide–semiconductor (PMOS) transistor and a first n-channel metal–oxide–semiconductor (NMOS) transistor connected in series between a power supply voltage and an input node of the sense amplifier;
- a second NMOS transistor connected between the input node and a ground;
- a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series between the power supply voltage and the ground;
- a first switch connected between a first node between the first PMOS transistor and the first NMOS transistor and a second node between the second PMOS transistor and the third NMOS transistor;
- and
- a second switch connected between the second node and an output node of the sense amplifier,
- wherein a gate electrode of the first PMOS transistor is connected to the ground,
- wherein a gate electrode of the first NMOS transistor is connected to the power supply voltage,
- wherein a gate electrode of the second NMOS transistor is connected to the input node, and
- wherein a gate electrode of the second PMOS transistor is connected to the first node.
A memory device comprising:
- a memory cell array comprising a plurality of memory cells connected to a first read bit line;
- and
- a sense amplifier connected to the first read bit line,
- wherein the sense amplifier comprises:
- a first p-channel metal–oxide–semiconductor (PMOS) transistor, a first n-channel metal–oxide–semiconductor (NMOS) transistor, and a second NMOS transistor connected in series between a power supply voltage and a ground;
- a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor connected in series between the power supply voltage and the ground;
- and
- a first switch connected between a first node between the first PMOS transistor and the first NMOS transistor and a second node between the second PMOS transistor and the third NMOS transistor,
- wherein a gate electrode of the first PMOS transistor is connected to the ground,
- wherein a gate electrode of the first NMOS transistor is connected to the power supply voltage, and
- wherein a gate electrode of the second PMOS transistor is connected to the first node.
A sense amplifier which is connected to a plurality of memory cells, comprising:
- a first p-channel metal–oxide–semiconductor (PMOS) transistor, a first n-channel metal–oxide–semiconductor (NMOS) transistor, and a second NMOS transistor connected in series between a power supply voltage and a ground;
- a first switch connected between a first node between the first PMOS transistor and the first NMOS transistor and a second node;
- a second PMOS transistor connected between the power supply voltage and the second node;
- and
- a second switch connected between the second node and an output node,
- wherein the first switch is turned on based on a reset signal, and
- wherein, while the first switch is turned on, the first node and the second node are connected and a voltage of the first node changes from the power supply voltage to a first voltage based on a characteristic of the second PMOS transistor.
Dependencies are inferred from the claim text.