Abstract
A body bias generation circuit supplies a body region of a PMOS transistor with a body potential. The body potential is applied so that the body region may be reversely biased or not biased relative to the source region in response to an input signal. The input signal is inputted so that the zero bias may be applied to the body region during standby of the PMOS transistor and the reverse bias may be applied during operation. A body bias generation circuit supplies a body region of an NMOS transistor with a body potential in response to an inverted signal of the input signal. With this constitution, a leak current during standby can be suppressed.
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