G11C 29/56012
Timing aspects, clock generation, synchronisation
Official title: {Timing aspects, clock generation, synchronisation}
G11C29/56012 (Timing aspects, clock generation, synchronisation) appears on 325 US grants and 350 published applications in this corpus.
Search patents in G11C- Granted patents
- 325
- Published applications
- 350
- Assignees
- 135
- Inventors
- 711
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1997 | 2 | 0 |
| 1998 | 0 | 0 |
| 1999 | 6 | 0 |
| 2000 | 2 | 0 |
| 2001 | 0 | 0 |
| 2002 | 3 | 5 |
| 2003 | 7 | 11 |
| 2004 | 10 | 14 |
| 2005 | 7 | 13 |
| 2006 | 9 | 21 |
| 2007 | 24 | 19 |
| 2008 | 16 | 11 |
| 2009 | 15 | 11 |
| 2010 | 9 | 12 |
| 2011 | 11 | 15 |
| 2012 | 11 | 15 |
| 2013 | 12 | 4 |
| 2014 | 7 | 9 |
| 2015 | 7 | 9 |
| 2016 | 9 | 6 |
| 2017 | 14 | 21 |
| 2018 | 13 | 13 |
| 2019 | 12 | 18 |
| 2020 | 25 | 22 |
| 2021 | 27 | 15 |
| 2022 | 14 | 31 |
| 2023 | 16 | 16 |
| 2024 | 22 | 12 |
| 2025 | 8 | 11 |
| 2026 | 7 | 16 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Motherboard for testing memory modules in the presence of failures6 Oct 2026US 12,755,810 B2Intelligent Memory Limited
- Write latency testing systems and methods23 Jun 2026US 12,665,042 B2Advantest Corporation
- Signal skew correction in integrated circuit memory devices26 May 2026US 12,640,224 B2Rambus Inc.
- Device and method for testing memory28 Apr 2026US 12,614,604 B2Hprobe
- Electronic device including DRAM and method for operating the same24 Mar 2026US 12,586,658 B2Samsung Electronics Co., Ltd.
- Receiving device and data jitter suppression method thereof17 Sep 2026US 2026/0279483 A1Macronix International Co., Ltd.
- Method of setting signal drive strength of storage13 Aug 2026US 2026/0237453 A1Atp Electronics Taiwan Inc.
- Method for determining timing parameter of memory chip, controller, device, and medium30 Jul 2026US 2026/0221211 A1Shenzhen Rayson Technology Co., Ltd.
- Semiconductor device, control method for semiconductor device and control program25 Jun 2026US 2026/0179714 A1Renesas Electronics Corporation
- Storage controller performing odt training, method of operating the same, and method of operating storage system including the same25 Jun 2026US 2026/0179715 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Method for apparatus for tracking errors in a memory system111US 6,560,725 B1Madrone Solutions, Inc. · 2003
- Testing method and testing apparatus52US 7,358,714 B2Fujitsu Limited · 2008
- Method and apparatus for testing high performance circuits45US 6,510,534 B1LogicVision, Inc. · 2003
- Built-in self-test arrangement for integrated circuit memory devices37US 5,883,843 ATexas Instruments Incorporated · 1999
- Synchronization point across different memory BIST controllers34US 7,036,064 B12006