US 6,510,534 B1 · Method and apparatus for testing high performance circuits

Abstract

A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out. A test controller is clocked a test clock and includes a clock generation module for generating shift and capture clocks. The test clock can be an independent and asynchronous clock or derived from the system clock. The test can also be performed by using only the test clock in the case only the test clock is available or for diagnostic and debug purposes.

Claims44

Dependent claims

A method of performing an at-speed test, using a test clock and a system clock, of a circuit having combinational logic and scannable, clocked scan type memory elements having a capture clock input and a shift clock input, said method comprising:

configuring said circuit in an active or an inactive initialization mode;
when said circuit is configured in an active initialization mode,
disabling any sequential loops associated with non-scannable memory elements in said combinational logic;
disabling analysis of test response data;
performing a predetermined number of initialization cycles including:
loading initialization data into said scannable memory elements under the control of a clock signal derived from one of a test clock and a system clock;
and
performing a capture cycle under the control of a clock signal derived from one of a test clock and a system clock;
deactivating said initialization signal;
and
enabling any disabled sequential loops in said combinational logic;
loading a test stimulus into said scannable memory elements under the control of a shift clock signal derived from said test clock;
performing a capture operation under the control of a capture clock derived from one of said test clock and a free running system clock for a predetermined number of cycles of said capture clock;
enabling analysis of test response data;
and
unloading test response data from said scannable memory elements under the control of said shift clock signal.

13 more elements

A method of performing an at-speed test of a circuit having combinational logic and scannable, clocked scan type memory elements using a free-running test clock and a free running system clock, each said scannable memory elements having a capture clock input, a shift clock input, said method comprising:

generating an active Scan Enable signal, an initialization signal, a capture clock control signal;
while said initialization signal is active, performing a predetermined number of non-scannable memory element initialization cycles, including:
enabling a shift clock derived from said free running test clock in response to said active Scan Enable signal;
loading initialization data into said scannable memory elements according to a shift sequence under the control of said shift clock;
deactivating said Scan Enable signal and disabling said shift clock in response to said inactive Scan Enable signal;
enabling a capture clock derived from one of said test and system clocks in response to said inactive Scan Enable signal;
applying one clock cycle of said capture clock;
deactivating said initialization signal when all non-scannable memory elements in said circuit have been initialized;
loading a test stimulus into said scannable memory elements according to a shift sequence including:
generating an active scan enable signal;
enabling a shift clock derived from said free running test clock in response to said active Scan Enable signal;
serially shifting said test stimulus into said scannable memory elements under the control of said shift clock;
deactivating said Scan Enable signal;
and
disabling said shift clock in response to said inactive Scan Enable signal;
performing a capture operation including:
selecting one of said test and system clocks as a capture clock;
delaying enabling said capture clock while said capture clock control signal is active;
enabling said capture clock for at least two clock cycles thereof;
unloading test response data from said scannable memory elements including:
generating an active scan enable signal;
enabling said shift clock derived from said free running test clock in response to said active Scan Enable signal;
serially shifting said test response data from said scannable memory elements under the control of said shift clock;
and
analyzing said test response data.

22 more elements

A method of performing an at-speed test of a circuit having combinational logic and scannable, clocked scan type memory elements each said scannable memory elements having a capture clock input, a shift clock input, said method comprising:

configuring said circuit in an active or an inactive debug mode;
configuring said circuit in an active or an inactive initialization mode;
when said circuit is configured in an inactive debug mode,
when said circuit is configured in an active initialization mode,
disabling any sequential loops associated with non-scannable memory elements in said combinational logic;
initializing non-scannable memory elements in said circuit including:
disabling analysis of test response data;
iteratively loading initialization data into said scannable memory elements and then performing a capture cycle under the control of a shift clock derived from one of a free running test clock and a free running system clock until completion of initialization of non-scannable memory elements in said circuit with known values and then deactivating said initialization signal;
enabling analysis of test response data;
and
enabling any disabled sequential loops in said combinational logic
loading a test stimulus into said scannable memory elements under the control of a shift clock signal derived from one of said a free running test clock and a free running system clock;
performing a capture operation under the control of a capture clock derived from said system clock and a free running system clock for a predetermined number of cycles of said capture clock;
unloading test response data from said scannable memory elements under the control of said shift clock;
when said circuit is configured in an inactive initialization mode,
loading a test stimulus into said scannable memory elements under the control of a shift clock signal derived from one of said a free running test clock and a free running system clock;
performing a capture operation under the control of a capture clock derived from one of said test clock and a free running system clock for a predetermined number of cycles of said capture clock;
and
unloading test response data from said scannable memory elements under the control of said shift clock;
when said circuit is configured in an active debug mode,
when said circuit is configured in an active initialization mode,
initializing non-scannable memory elements in said circuit including:
disabling any sequential loops associated with non-scannable memory elements in said combinational logic;
disabling analysis of test response data;
iteratively loading initialization data into said scannable memory elements and then performing a capture cycle under the control of a shift clock derived from a free running test clock until completion of initialization of non-scannable memory elements in said circuit with known values and then deactivating said initialization signal;
enabling analysis of test response data;
enabling any disabled sequential loops in said combinational logic;
and
loading a test stimulus into said scannable memory elements under the control of a shift clock signal derived from one of said free running test clock and a free running system clock;
performing a capture operation under the control of a capture clock derived from said test clock for a predetermined number of cycles of said capture clock;
unloading test response data from said scannable memory elements under the control of said shift clock;
when said circuit is configured in an inactive initialization mode,
loading a test stimulus into said scannable memory elements under the control of a shift clock signal derived from said free running test clock;
performing a capture operation under the control of a capture clock derived from said test clock for a predetermined number of cycles of said capture clock;
and
unloading test response data from said scannable memory elements under the control of said shift clock;
and
analyzing and validating said response data.

35 more elements

A BIST controller for an integrated circuit having combinational logic and scannable clocked scan type memory elements connected to said combinational logic and having a capture clock input, a shift clock input, a data input, a data output, a serial data input and a serial data output, said controller comprising:

a control circuit for generating a scan enable signal and an initialization control signal;
a clock generating circuit for receiving a test clock and a system clock and for generating a shift clock and a capture clock;
means responsive to an active scan enable signal and said test clock for generating a test stimulus and serially loading said test stimulus into said scannable memory elements;
and
means responsive to an inactive initialization control signal and an active scan enable signal for analysing test response data unloaded from said scannable memory elements;
said clock generating circuit including:
means for producing said shift clock, said means for producing having a shift clock output and a test clock input and being responsive to an active scan enable signal for connecting said test clock input to said shift clock output and responsive to an inactive scan enable signal for disabling said shift clock output;
and
means for generating said capture clock having a test clock input, a system clock input and a capture clock output and being responsive to an inactive scan enable signal and an active initialization control signal for connecting one of said test and system clocks to said capture clock output for one clock cycle of said capture clock and responsive to an inactive scan enable signal and an inactive initialization signal for connecting said system clock input to said capture clock output for at least two cycles of said capture clock.

6 more elements

a control circuit for generating a scan enable signal and an initialization control signal;
a clock generating circuit for receiving a test clock and a system clock and for generating a shift clock and a capture clock;
means responsive to an active scan enable signal and said test clock for generating a test stimulus and serially loading said test stimulus into said scannable memory elements;
and
means responsive to an inactive initialization control signal and an active scan enable signal for analysing test response data unloaded from said scannable memory elements;
said clock generating circuit including:
means for producing said shift clock, said means for producing having a shift clock output and a test clock input and being responsive to an active scan enable signal for connecting said test clock input to said shift clock output and responsive to an inactive scan enable signal for disabling said shift clock output;
and
means for generating said capture clock responsive to an inactive scan enable signal and an active initialization control signal for connecting one of said test and system clocks to said capture clock output for one clock cycle of said capture clock and responsive to an inactive scan enable signal and an inactive initialization signal for connecting said system clock input to said capture clock output for at least two cycles of said capture clock and further including:
a test clock input,
a system clock input;
a capture clock output;
delay means for producing a capture clock control signal for delaying enabling of said capture clock for a predetermined time interval following said scan enable signal becoming inactive;
transition detection means responsive said capture clock control signal for detecting a transition from active to inactive of said capture clock control signal for producing a capture clock enable signal enabling said capture clock;
and
means receiving said system clock and responsive to an active capture clock enable signal for connecting said system clock to said capture clock output.

13 more elements

In an integrated circuit having combinational logic and scannable clocked scan type memory elements connected to said combinational logic and having a capture clock input, a shift clock input, a data input, a data output, a serial data input and a serial data output, the improvement comprising:

a BIST controller having:
a control circuit for generating a scan enable signal and an initialization control signal;
a clock generating circuit for receiving a test clock and a system clock and for generating a shift clock and a capture clock;
means responsive to an active scan enable signal and said test clock for generating a test stimulus and serially loading said test stimulus into said scannable memory elements;
and
means responsive to an inactive initialization control signal and an active scan enable signal for analysing test response data unloaded from said scannable memory elements;
said clock generating circuit including:
means for producing said shift clock, said means for producing having a shift clock output and a test clock input and being responsive to an active scan enable signal for connecting said test clock input to said shift clock output and responsive to an inactive scan enable signal for disabling said shift clock output;
and
means for generating said capture clock having a test clock input, a system clock input and a capture clock output and being responsive to an inactive scan enable signal and an active initialization control signal for connecting one of said test and system clocks to said capture clock output and responsive to an inactive scan enable signal and an inactive initialization signal for connecting said system clock input to said capture clock output for at least two cycles of said capture clock;
and
said combinational logic means responsive to an active initialization signal for disabling any sequential loops associated with non-scannable memory elements in said combinational logic and responsive to an inactive initialization signal for enabling any disabled sequential loops associated with non-scannable memory elements in said combinational logic.

9 more elements

Dependencies are inferred from the claim text.

Method and apparatus for testing high performance circuits

Life of this patent

Method and apparatus for testing high performance circuits

Life of this patent

Abstract

Claims44