Built-in self-test arrangement for integrated circuit memory devices
AssigneeTexas Instruments Incorporated
InventorsKuong Hua Hii, Danny R. Cline, Theo J. Powell
Life of this patent
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Abstract
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
Claims6
An integrated circuit having a built-in self test (BIST) arrangement, comprising:
- a built-in self-test detector, responsive to an input signal on an address pin, for placing an integrated circuit into a standby mode and further responsive to another input signal for placing the integrated circuit into a self-test mode;
- a read only memory storing test algorithm instructions;
- a logic circuit, interconnected with the read only memory, for receiving an instruction read from the read only memory and producing at an output terminal a group of output signals dependent upon the instruction;
- a BIST register, connected with the output terminal for receiving and storing the group of output signals from the logic circuit.
An integrated circuit memory array device having a built-in self-test (BIST) arrangement, the memory device comprising:
- an address buffer for receiving and storing a sequence of addresses;
- a built-in self-test detector, responsive to input signals, for controlling operation of the device alternatively in either a normal mode or a self-test mode at least one input signal occurring on an address line;
- address range registers, arranged for receiving and storing start and end addresses, for a self-test operation of the memory array while the device is operating in the self-test mode;
- and
- a self-test address counter, interconnected with the address range registers and the address buffer, for applying to the address buffer a sequence of addresses commencing with the start address and stopping at the end address.
Dependencies are inferred from the claim text.