Motherboard for testing memory modules in the presence of failures
AssigneeIntelligent Memory Limited
InventorPeter Poechmueller
Life of this patent
Estimating the term…
Abstract
A motherboard assembly for testing memory components is described. The motherboard assembly has at least one CPU communicatively coupled with at least one memory channel, and a memory controller or BIOS programmed to continue booting in the presence of memory component failures. The memory controller or BIOS skips read/write training procedures when a failure is detected, and uses preset values for PHY registers from a previous successful booting procedure to continue the current booting without powering off. The memory controller or BIOS is also programmed to provide adjustable retention settings and adjustable speed settings without rebooting or powering off.
Claims20
A motherboard assembly for memory component testing, comprising:
- at least one CPU;
- at least one memory channel;
- at least one electrical connection that communicatively couples the CPU and the memory channel;
- a memory controller or BIOS programmed to:
- (a) skip write leveling, MPR pattern write, read centering, and write centering procedures in presence of a memory component failure, and use preset values for PHY registers from a previous successful booting procedure to continue current booting without powering off;
- (b) provide adjustable retention settings without rebooting or powering off;
- and
- (c) provide adjustable speed settings without rebooting or powering off.
A motherboard assembly for memory component testing, comprising:
- at least one FPGA;
- at least one memory channel;
- at least one electrical connection that communicatively couples the CPU and the memory channel;
- a memory controller or BIOS programmed to:
- (a) skip write leveling, MPR pattern write, read centering, and write centering procedures in presence of a memory component failure, and use preset values for PHY registers from a previous successful booting procedure to continue current booting without powering off;
- and
- (b) provide adjustable retention settings without rebooting or powering off;
- and
- (c) provide adjustable speed settings without rebooting or powering off.
A motherboard assembly for memory component testing, comprising:
- a frame dimensioned to receive an upper motherboard and a lower motherboard;
- at least one memory channel disposed on the upper motherboard;
- a gap vertically separating the upper motherboard from the lower motherboard;
- at least one CPU or FPGA disposed on the lower motherboard;
- at least one electronic connector communicatively coupling the at least one CPU or FPGA with the at least one memory channel;
- and
- a memory controller or BIOS programmed to:
- (a) skip write leveling, MPR pattern write, read centering, and write centering procedures in presence of a memory component failure, and use preset values for PHY registers from a previous successful booting procedure to continue current booting without powering off;
- and
- (b) provide adjustable retention settings without rebooting or powering off;
- and
- (c) provide adjustable speed settings without rebooting or powering off.
Dependencies are inferred from the claim text.