Signal skew correction in integrated circuit memory devices
AssigneeRambus Inc.
InventorsSrinivas Satish Babu Bamdhamravuri, Panduka Wijetunga
Life of this patent
Estimating the term…
Abstract
Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.
Claims7
An integrated circuit memory device comprising:
- a first interface configured to receive command/address (CA) signals and a clock signal, the first interface having a receiver for each of the CA signals;
- a data interface, wherein the first interface, in a CA bus loopback mode, is configured to receive a pattern of CA signals and the data interface, in the CA bus loopback mode, is configured to output the received pattern of CA signals;
- a mode register configured to store values representative of a timing offset between the clock signal and a sampling point for the first interface, wherein the values include a first value and a second value;
- a first delay element controlled by the first value stored in the mode register to delay a clock edge by a first programmable delay;
- and
- a plurality of delay elements, wherein each delay element is controlled by the second value stored in the mode register to delay a sampling point for each receiver of the first interface, for each corresponding CA signal, by a second programmable delay.
Dependencies are inferred from the claim text.