G11C 29/38
Response verification devices
G11C29/38 (Response verification devices) appears on 3,322 US grants and 3,357 published applications in this corpus.
Search patents in G11C- Granted patents
- 3,322
- Published applications
- 3,357
- Assignees
- 475
- Inventors
- 4,994
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 2 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 4 | 0 |
| 1988 | 2 | 0 |
| 1989 | 3 | 0 |
| 1990 | 9 | 0 |
| 1991 | 7 | 0 |
| 1992 | 6 | 0 |
| 1993 | 9 | 0 |
| 1994 | 8 | 0 |
| 1995 | 16 | 0 |
| 1996 | 20 | 0 |
| 1997 | 16 | 0 |
| 1998 | 23 | 0 |
| 1999 | 34 | 0 |
| 2000 | 16 | 0 |
| 2001 | 21 | 11 |
| 2002 | 32 | 34 |
| 2003 | 29 | 36 |
| 2004 | 34 | 50 |
| 2005 | 28 | 60 |
| 2006 | 53 | 62 |
| 2007 | 63 | 62 |
| 2008 | 52 | 67 |
| 2009 | 52 | 40 |
| 2010 | 45 | 34 |
| 2011 | 51 | 42 |
| 2012 | 35 | 38 |
| 2013 | 44 | 45 |
| 2014 | 63 | 102 |
| 2015 | 98 | 135 |
| 2016 | 129 | 176 |
| 2017 | 173 | 185 |
| 2018 | 147 | 159 |
| 2019 | 197 | 257 |
| 2020 | 279 | 278 |
| 2021 | 271 | 286 |
| 2022 | 304 | 353 |
| 2023 | 328 | 272 |
| 2024 | 292 | 253 |
| 2025 | 204 | 188 |
| 2026 | 114 | 132 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cascade model for determining read level voltage offsets based on wordline group memory cells29 Sep 2026US 12,749,541 B2Micron Technology, Inc.
- System and method for conducting built-in self-test of memory macro29 Sep 2026US 12,749,552 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Transmission failure feedback schemes for reducing crosstalk22 Sep 2026US 12,743,338 B2
- Unmatched data path delay compensation for non-volatile memory22 Sep 2026US 12,744,099 B2SanDisk Technologies LLC
- Memory device and memory testing22 Sep 2026US 12,744,100 B2Sigmastar Technology Ltd.
- Optimization of soft bit windows based on signal and noise characteristics of memory cells8 Oct 2026US 2026/0311755 A1Micron Technology, Inc.
- Self-calibration in a memory device8 Oct 2026US 2026/0311791 A1Micron Technology, Inc.
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- System and method for conducting built-in self-test of memory macro1 Oct 2026US 2026/0301839 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Onboard control system24 Sep 2026US 2026/0290484 A1Astemo, Ltd.
Most cited
By later US patents
- Method and apparatus for memory array compressed data testing482US 5,935,263 AMicron Technology, Inc. · 1999
- Semiconductor memory device432US 5,724,366 AMitsubishi Denki Kabushiki Kaisha · 1998
- Semiconductor memory device having multi-bit testing function424US 6,816,422 B2Renesas Technology Corp. · 2004
- Data path having grounded precharge operation and test compression capability423US 7,061,817 B2Micron Technology, Inc. · 2006
- Use of hashing function to distinguish random and repeat errors in a memory system419US 8,347,154 B2International Business Machines Corporation · 2013