Memory device and memory testing

A memory testing method, comprising:

• generating, by a pattern generating circuit, test pattern data, a test address and reference data;
• performing, by a plurality of memory modules, a built-in self-test (BIST) according to the test pattern data, the test address and the reference data to generate a plurality of test results;
• generating an indicator signal according to the plurality of test results;
• when a first test result among the plurality of test results indicates a fault, retaining, by the pattern generating circuit, the test address in response to the indicator signal, and testing, according to the test address and a plurality of sets of predetermined pattern data, a first memory module among the plurality of memory modules that corresponds to the first test result to generate a localization test result;
• and
• determining a faulty memory cell in the first memory module according to the localization test result,
• wherein when the first test result among the plurality of test results indicates a fault, the retaining of, by the pattern generating circuit, the test address in response to the indicator signal, and testing, according to the test address and a plurality of sets of predetermined pattern data, a first memory module among the plurality of memory modules that corresponds to the first test result to generate a localization test result comprises:
• generating the localization test result based on a weighting sum from a stuck-at fault of the faulty memory cell and the plurality of sets of predetermined pattern data.

A memory device, comprising:

• a pattern generating circuit, generating test pattern data, a test address and reference data;
• a plurality of memory modules, performing a built-in self-test (BIST) according to the test pattern data, the test address and the reference data to generate a plurality of test results;
• and
• a logic circuit, generating an indicator signal according to the plurality of test results;
• wherein, when a first test result among the plurality of test results indicates a fault, the pattern generating circuit retains the test address in response to the indicator signal, and tests, according to the test address and a plurality of sets of predetermined pattern data, a first memory module among the plurality of memory modules that corresponds to the first test result, so as to determine a faulty memory cell in the first memory module according to a localization test result generated by the first memory module based on the plurality of sets of predetermined pattern data,
• wherein the pattern generating circuit comprises:
• a register;
• a pattern control circuit, configured by the register to generate the test pattern data, the test address, the reference data and the plurality of sets of predetermined pattern data;
• and
• a data collecting circuit, configuring the register according to the indicator signal for the pattern control circuit to retain the test address.