Method and apparatus for memory array compressed data testing

A method of transferring data from a memory array within a memory device to a data bus, comprising:

• reading a plurality of data from the memory array;
• determining, within the memory device, if any of the read data correspond to an error;
• if any of the read data correspond to an error, producing a flag signal having a first logic state indicating the presence of an error and a second logic state indicating the absence of an error;
• transferring the flag signal to an output driver circuit;
• if the flag signal has the second logic state, outputting the read data from the output driver circuit during an output interval;
• and
• if the flag signal has the first logic state producing an error indicator from the output driver circuit during the output interval.

A method of transferring data from a memory array to a data bus, comprising:

• segmenting the data from the array into groups, each group containing a plurality of bits;
• if any of the bits in a selected one of the groups corresponds to an error at the memory array, selectively blocking the selected group of data from the data bus;
• and
• if none of the bits in the selected one of the groups corresponds to an error at the memory array, transferring the group of data to the data bus.

A method of testing a memory device responsive to a clock signal, the memory device including a memory array comprising the steps of:

• writing data to the memory array in a predetermined pattern;
• after writing data to the memory array issuing a read command on a first clock transition;
• at a second clock transition and responsive to the read command reading data from the memory array;
• within the memory device comparing the data read from the memory array to the predetermined pattern;
• producing an output signal responsive to the step of comparing the data read from the memory array to the predetermined pattern;
• and
• at a plurality of clock transitions outputting the output signal from the memory device.

A memory device, comprising:

• an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal;
• a memory array arranged in rows and columns;
• an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells within the memory array, the I/O interface including a plurality of output terminals;
• a data path coupled between the I/O interface and the output driver circuit;
• and
• a comparing circuit having an input coupled to the data path and an error output terminal coupled to the error input terminal, the comparing circuit being responsive to compare data on the data path to a selected set of data and to produce the error signal at the error output terminal in response to the data on the data path not matching the selected set of data.

A test system including:

• a data bus;
• a memory device including:
• an output driver circuit having a data output terminal coupled to the data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal at the data output terminal in response to an error signal at the error input terminal;
• a memory array arranged in rows and columns;
• an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells within the memory array, the I/O interface including a plurality of output terminals;
• a data path coupled between the I/O interface and the output driver circuit;
• and
• a comparing circuit having an input coupled to the data path and an error output terminal coupled to the error input terminal, the comparing circuit being responsive to compare data on the data path to a selected set of data and to produce the error signal at the error output terminal in response to the data on the data path not matching the selected set of data;
• a test head adapted for coupling to the output driver circuit, the test head being responsive to detect the tri-state condition;
• and
• testing circuitry coupled to the test head.