System and method for conducting built-in self-test of memory macro

A built-in self-test circuit comprising:

• a memory having computer-readable instructions stored thereon;
• and
• a processor that executes the computer-readable instructions to:
• generate and transmit an input vector to a memory macro;
• generate a plurality of weights for writing to a first half of the memory macro and writing a 2's complement of the plurality of weights to a second half of the memory macro;
• receive an output data generated by the memory macro in response to performing a multiply-and-accumulate operation between the input vector and the plurality of weights and the input vector and the 2's complement of the plurality of weights;
• compare the output data with a signature value;
• and
• determine whether the memory macro is normal or faulty based upon a comparison.

A method comprising:

• generating, by a built-in self-test circuit, an input vector for transmission to a memory macro for testing the memory macro, the input vector comprising a partial input vector of half a bit width designated for the input vector;
• transmitting the partial input vector to each of a first half of the memory macro and a second half of the memory macro;
• generating a plurality of weights for transmission to the first half of the memory macro and a 2's complement of the plurality of weights for transmission to the second half of the memory macro;
• receiving first output data generated by the memory macro in response to performing a first multiply-and-accumulate operation between the partial input vector and the plurality of weights;
• receiving second output data generated by the memory macro in response to performing a second multiply-and-accumulate operation between the partial input vector and the 2's complement of the plurality of weights;
• and
• computing a sum of the first output data and the second output data;
• and determining that the memory macro is normal based upon the sum being a predetermined value.