G11C 2207/2272
Latency related aspects
G11C2207/2272 (Latency related aspects) appears on 450 US grants and 477 published applications in this corpus.
Search patents in G11C- Granted patents
- 450
- Published applications
- 477
- Assignees
- 92
- Inventors
- 593
- Latest grant
- 26 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2005 | 0 | 2 |
| 2006 | 1 | 2 |
| 2007 | 1 | 1 |
| 2008 | 4 | 11 |
| 2009 | 7 | 11 |
| 2010 | 4 | 16 |
| 2011 | 13 | 20 |
| 2012 | 20 | 19 |
| 2013 | 23 | 22 |
| 2014 | 19 | 25 |
| 2015 | 22 | 19 |
| 2016 | 26 | 19 |
| 2017 | 19 | 24 |
| 2018 | 32 | 24 |
| 2019 | 30 | 52 |
| 2020 | 44 | 32 |
| 2021 | 40 | 42 |
| 2022 | 35 | 40 |
| 2023 | 36 | 36 |
| 2024 | 32 | 26 |
| 2025 | 34 | 18 |
| 2026 | 8 | 16 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Semiconductor memory device employing processing in memory (PIM) and method of operating the semiconductor memory device26 May 2026US 12,639,037 B2Samsung Electronics Co., Ltd.
- Buffer chip, semiconductor package including buffer chip and memory chip, memory module, and operation method of semiconductor package26 May 2026US 12,640,175 B2SK hynix Inc.
- Latency optimized eviction allocation for memories17 Mar 2026US 12,579,077 B2Arm Limited
- Storage and access of data and tags in a multi-way set associative cache24 Feb 2026US 12,561,251 B2Rambus Inc.
- Clocking architecture supporting multiple data rates and reference edge selection17 Feb 2026US 12,555,621 B1Rambus Inc.
- Memory module power control apparatus and memory power control apparatus24 Sep 2026US 2026/0290424 A1
- Memory apparatus having buffer die24 Sep 2026US 2026/0293162 A1SK hynix Inc.
- Signal development caching in a memory device2 Jul 2026US 2026/0186709 A1Micron Technology, Inc.
- Non-volatile memory device and method for simultaneously reading two memory banks21 May 2026US 2026/0140635 A1STMicroelectronics International N. V.
- Accelerated in-memory cache with memory array sections having different configurations21 May 2026US 2026/0140877 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Output enable signal generation circuit of semiconductor memory1,017US 8,400,851 B2SK hynix Inc. · 2013
- Memory access system and method using de-coupled read and write circuits193US 7,466,607 B2Analog Devices, Inc. · 2008
- System and method for power management in memory systems138US 7,590,796 B2Metaram, Inc. · 2009
- Interface circuit system and method for performing power saving operations during a command-related latency134US 7,581,127 B2Metaram, Inc. · 2009
- Semiconductor memory apparatus90US 8,856,410 B2SK hynix Inc. · 2014