Clocking architecture supporting multiple data rates and reference edge selection

A method for operating a buffer circuit comprising:

• receiving, by an internal clock generator circuit, an input clock from a source device, the input clock providing timing information associated with an input data signal, and receiving by the internal clock generator circuit, an internal clock control signal specifying a first selected reference edge of the input clock;
• generating, by the internal clock generator circuit, an internal clock locked to the first selected reference edge of the input clock;
• receiving the input clock at an output clock generator circuit;
• generating, by the output clock generator circuit, an output clock locked to the input clock, wherein the output clock has a predefined phase relationship to the input clock that is independent of the first selected reference edges;
• receiving, by a sampler circuit, the input data signal from the source device;
• sampling, by the sampler circuit, the input data signal based on the internal clock to generate an output data signal;
• and
• outputting, by an output interface, the output data signal with the output clock to a destination device, wherein the output clock provides timing information associated with the output data signal.

A memory module comprising:

• a memory device;
• a data interface to receive write data for writing to the memory device in a write operation or read data read from the memory device in a read operation;
• a command/address interface to receive an input data signal from a source device comprising command and address data associated with the read and write operations of the memory device;
• a clock interface to receive an input clock from the source device, the input clock providing timing information associated with the input data signal;
• a buffer circuit comprising:
• an internal clock generator circuit to receive the input clock and an internal clock control signal specifying a first selected reference edge of the input clock, and to generate an internal clock locked to the first selected reference edge of the input clock;
• an output clock generator circuit to receive the input clock, and to generate an output clock locked to the input clock, wherein the output clock has a predefined phase relationship to the input clock that is independent of the first selected reference edge;
• a sampling circuit to receive the input data signal from the source device and to sample the input data signal based on the internal clock to generate an output data signal;
• and
• an output interface to output the output data signal and to output the output clock to a destination device, wherein the output clock provides timing information associated with the output data signal.