Storage and access of data and tags in a multi-way set associative cache
AssigneeRambus Inc.
InventorsThomas Vogelsang, Frederick A. Ware, Michael Raymond Miller, Collins Williams
Life of this patent
Estimating the term…
Abstract
Disclosed is a dynamic random access memory (DRAM) that includes a plurality of data rows and a plurality of tag rows. The DRAM includes a communication interface to receive a first group of address bits. The DRAM includes one or more comparators to generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the plurality of tag rows. The one or more comparators are further to combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.
Claims20
A dynamic random access memory (DRAM), the DRAM comprising:
- a plurality of data rows and a plurality of tag rows;
- a communication interface to receive a first group of address bits;
- and
- one or more comparators to:
- generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the plurality of tag rows;
- and
- combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.
A set associative cache dynamic random access memory (DRAM), comprising:
- one or more banks, each bank comprising a plurality of mats, each mat comprising a plurality of DRAM cells in rows and columns;
- a majority of the rows comprising rows for data as data rows, a minority of the rows comprising rows for tags, as tag rows;
- a communication interface to receive a first group of address bits;
- and
- one or more comparators each to:
- generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the tag rows;
- and
- combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.
A method of operating a set associative cache dynamic random access memory (DRAM), comprising:
- presenting a first group of address bits of a set in the DRAM to each of one or more comparators inside one or more banks of the DRAM, wherein each bank has data rows and tag rows;
- generating a tag match indication and one or more set bits;
- and
- combining, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.
Dependencies are inferred from the claim text.