Non-volatile memory device and method for simultaneously reading two memory banks

A method for reading data units in a memory device comprising the steps of:

• receiving by a memory interface read commands from a host device;
• transmitting by the memory interface to a non-volatile memory (NVM) controller a first read command of a data unit, the first read command indicating a first read memory address;
• and
• in response to the first read command:
• simultaneously reading by the NVM controller a first data unit at a memory address of a first bank of a non-volatile memory corresponding to the first read memory address and reading a second data unit at the same memory address of a second bank of the non-volatile memory;
• and
• transmitting by the NVM controller the read first data unit to the memory interface and storing the second data unit in a data register of the NVM controller.

A memory device clocked by clock cycles, comprising:

• a memory interface configured to receive instructions to read four N/2-bit words from a host device and to send data read from memory on a system bus of N/2 bits to the host device;
• an memory controller connected to at least two non-volatile memory banks storing data on N bits;
• wherein the memory controller is configured to receive, from the memory interface, a first command to read a data unit of N bits followed by a second command to read a data unit of N bits, the first command indicating a first read memory address and the second command indicating a second read memory address;
• and
• wherein the memory controller is further configured, in response to the first command, to:
• simultaneously read a first data unit of N bits to a store memory address in a first of the non-volatile memory stores that corresponds to the first read memory address and a second data unit of N bits to the same store memory address in the second non-volatile memory bank that corresponds to the second read memory address;
• transmit the first data unit read to the memory interface;
• and
• store the second data unit in a data register of the memory controller;
• and
• wherein the memory controller is further configured, in response to the second command received at a same clock cycle as the transmission of the first data unit, to:
• read the second data unit from the data register;
• and
• transmit, at a next clock cycle, the second unit of data is read from the memory interface;
• wherein the memory interface is configured to transmit two words to the host device on the system bus of N/2 bits corresponding to the first unit of data read followed by two words of N/2 bits corresponding to the second unit of data read, over four consecutive clock cycles.

A method for reading the units of data from a memory device clocked by clock cycles, the method comprising steps of:

• receiving, from a host device, through a memory interface four-word reading instructions of N/2 bits;
• transmitting through the memory interface to a memory controller a first command to read an N bit data unit followed by a second command to read an N bit data unit, the first read command indicating a first read memory address and the second command indicating a second read memory address;
• in response to the first command:
• simultaneously reading by the memory controller a first data unit of N bits to a memory address of a first bank of non-volatile memory corresponding to the first read memory address and reading a second data unit of N bits to the same memory address of a second bank of non-volatile memory which corresponds to the second read memory address;
• and
• transmitting the first data unit read from the memory controller to the memory interface;
• and
• storing the second data unit in a data register of the memory controller;
• and
• in response to the second command received at a same clock cycle as the transmission of the first data unit:
• reading the second data unit from the data register;
• and
• transmitting, at the next clock cycle, the second data unit read from the memory interface;
• and
• transmitting, through the memory interface to the host device on the system bus, two N/2-bit words corresponding to the first data unit read followed by two N/2-bit words corresponding to the second data unit read, over four consecutive clock cycles.