Latency optimized eviction allocation for memories

A memory circuitry for eviction allocation, the memory circuitry comprising:

• a memory array;
• read circuitry;
• write circuitry;
• and
• a control circuit coupled to the read circuitry and the write circuitry for operating the read circuitry and the write circuitry based on control inputs to the control circuit,
• wherein, in response to the control inputs indicating an eviction allocation operation comprising a read operation from a plurality of addresses and a write operation to a same plurality of addresses, the control circuit directs the read circuitry to read out a plurality of words from the plurality of addresses and, while the control circuit directs the read circuitry to read out the plurality of words, the control circuit directs the write circuitry to load a plurality of new words to be written to the same plurality of addresses into input registers of the write circuitry.