Back to results
US 2026/0293162 A1Published application
Memory apparatus having buffer die
AssigneeSK hynix Inc.
InventorSeong Ju LEE
Life of this patent
Estimating the term…
Abstract
A memory apparatus includes a package substrate, a plurality of memory dies, and a buffer die. The plurality of memory dies are connected to a data bus through the buffer die. The buffer die selectively connects the data bus to one or more of the memory dies based on a chip selection signal to reduce a capacitive load of the data bus.
Claims21
A memory apparatus comprising:
- a package substrate;
- a first memory die, a second memory die, a third memory die, and a fourth memory die sequentially disposed on the package substrate;
- and
- a buffer die disposed on the package substrate, connected to a first data bus and a second data bus, and configured, based on a chip selection signal, to connect the first data bus to one of the first memory die and the second memory die and connect the second data bus to one of the third memory die and the fourth memory die.
1 more element
A memory apparatus comprising:
- a package substrate;
- a buffer die disposed on the package substrate;
- a first memory die, a second memory die, a third memory die, and a fourth memory die sequentially disposed on the buffer die,
- wherein the buffer die is connected to a first data bus and a second data bus and, based on a chip selection signal, connects the first data bus to one of the first memory die and the second memory die and connects the second data bus to one of the third memory die and the fourth memory die.
1 more element
Dependencies are inferred from the claim text.