G11C 2029/0403
During or with feedback to manufacture
Official title: {during or with feedback to manufacture}
G11C2029/0403 (During or with feedback to manufacture) appears on 384 US grants and 374 published applications in this corpus.
Search patents in G11C- Granted patents
- 384
- Published applications
- 374
- Assignees
- 116
- Inventors
- 801
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 4 | 0 |
| 1993 | 1 | 0 |
| 1994 | 6 | 0 |
| 1995 | 4 | 0 |
| 1996 | 1 | 0 |
| 1997 | 3 | 0 |
| 1998 | 1 | 0 |
| 1999 | 4 | 0 |
| 2000 | 3 | 0 |
| 2001 | 3 | 2 |
| 2002 | 5 | 6 |
| 2003 | 10 | 8 |
| 2004 | 13 | 13 |
| 2005 | 13 | 21 |
| 2006 | 17 | 7 |
| 2007 | 7 | 8 |
| 2008 | 10 | 12 |
| 2009 | 7 | 4 |
| 2010 | 10 | 6 |
| 2011 | 5 | 5 |
| 2012 | 5 | 2 |
| 2013 | 2 | 3 |
| 2014 | 4 | 4 |
| 2015 | 10 | 8 |
| 2016 | 8 | 11 |
| 2017 | 13 | 18 |
| 2018 | 11 | 24 |
| 2019 | 27 | 35 |
| 2020 | 35 | 30 |
| 2021 | 30 | 35 |
| 2022 | 32 | 36 |
| 2023 | 26 | 30 |
| 2024 | 20 | 22 |
| 2025 | 23 | 19 |
| 2026 | 7 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Flash memory and testing method thereof15 Sep 2026US 12,738,340 B2Winbond Electronics Corp.
- Method to calculate performance of a magnetic element comprising a ferromagnetic layer exchange-coupled to an antiferromagnetic layer25 Aug 2026US 12,716,970 B2Allegro MicroSystems, LLC
- Heat dissipation in resistive memories11 Aug 2026US 12,707,903 B2Virginia Tech Intellectual Properties, Inc.
- Methods for fabricating 3D memory devices and structures with memory arrays and metal layers9 Jun 2026US 12,653,021 B2Monolithic 3D Inc.
- Methods for optimizing semiconductor device placement on a substrate for improved performance, and associated systems and methods12 May 2026US 12,626,731 B2Micron Technology, Inc.
- Apparatus including circuit usage detection mechanism and methods of manufacturing the same13 Aug 2026US 2026/0237451 A1Micron Technology, Inc.
- Stacked memory assembly with failure detection and repair4 Jun 2026US 2026/0155192 A1SanDisk Technologies LLC
- Silicon Wafer-Scale System, Repair Method Thereof, and Electronic Device7 May 2026US 2026/0129998 A1Huawei Technologies Co., Ltd.
- Dynamic random-access memory (dram) test pad arrangement method for a dram cell repair test on three-dimensional (3d) stacked dram26 Feb 2026US 2026/0060041 A1QUALCOMM Incorporated
- Computer system and method for operating data processing device12 Feb 2026US 2026/0045302 A1Semiconductor Energy Laboratory Co.Ltd.
Most cited
By later US patents
- Memory with isolatable expandable bit lines211US 5,677,867 A1997
- Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller193US 5,602,789 AKabushiki Kaisha Toshiba · 1997
- Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels167US 5,386,422 AKabushiki Kaisha Toshiba · 1995
- Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels138US 5,469,444 AKabushiki Kaisha Toshiba · 1995
- Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels125US 5,321,699 AKabushiki Kaisha Toshiba · 1994