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US 2026/0060041 A1Published application
Dynamic random-access memory (dram) test pad arrangement method for a dram cell repair test on three-dimensional (3d) stacked dram
AssigneeQUALCOMM Incorporated
InventorsWoo Tag KANG, Mustafa BADAROGLU, Jihong CHOI, Zhongze WANG, Giridhar NALLAPATI, Periannan CHIDAMBARAM
Life of this patent
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Abstract
A memory wafer is described. The memory wafer includes memory dies on the memory wafer. Additionally, the memory wafer includes wire connections at least partially within one of the memory dies. The wire connections are configured to couple to memory test and repair pads along at least one scribe line between the one of the memory dies and adjacent memory dies.
Claims20
A memory wafer, comprising:
- a plurality of memory dies on the memory wafer;
- and
- a plurality of wire connections at least partially within one of the plurality of memory dies, the plurality of wire connections configured to couple to a plurality of memory test and repair pads along at least one of a plurality of scribe lines between the one of the plurality of memory dies and adjacent memory dies.
A memory die, comprising:
- a memory cell array;
- and
- a plurality of wire connections to couple data DQ output pads and command connections of the memory cell array, in which each of the plurality of wire connections having a wire stub portion exposed along an edge of the memory die.
A method for a memory cell repair test during fabrication, the method comprising:
- probing a memory wafer using memory test and repair pads on scribe lines of the memory wafer to perform a test on memory dies residing on the memory wafer;
- verifying the memory wafer based on a result of the test;
- and
- performing wafer-to-wafer bonding of the memory wafer, if verified, and one or more verified memory wafers to form a memory wafer stack.
1 more element
Dependencies are inferred from the claim text.