Stacked memory assembly with failure detection and repair

A method comprising:

• applying a test pattern to a plurality of Deep Trench Contacts (DTCs) that extend through a stack of integrated memory assemblies;
• detecting one or more defective DTCs from electrical characteristics of the plurality of DTCs while applying the test pattern;
• and
• in response to detecting the one or more defective DTCs, replacing at least a portion of each defective DTC of the one or more defective DTCs by at least a portion of a redundant DTC.

A storage system, comprising:

• a stack of mirrored die pairs, each mirrored die pair including a first control die bonded to a first memory die, a second control die bonded to a second memory die and the first memory die bonded to the second memory die;
• a memory controller die that includes logic circuits configured to access memory cells in the stack of mirrored die pairs;
• a plurality of Deep Trench Contacts (DTCs) that extend through the stack of mirrored die to connect the memory controller die with each mirrored die pair, the plurality of DTCs including one or more redundant DTCs;
• and
• means for detecting one or more defective DTCs of the plurality of DTCs and replacing at least portions of the one or more defective DTCs by at least portions of redundant DTCs.