Flash memory and testing method thereof

A flash memory, comprising:

• a flash memory array, comprising a plurality of memory cells;
• and
• a memory control circuit, coupled to a plurality of word lines, a plurality of bit lines, and a plurality of source lines of the flash memory array, wherein the memory control circuit is configured to:
• adjust an erase verification current from a normal erase verification current to a fast bit screening erase verification current, and adjust a soft program verification current from a normal soft program verification current to a fast bit screening soft program verification current during a test, wherein the fast bit screening erase verification current is greater than the normal erase verification current, and the fast bit screening soft program verification current is less than the normal soft program verification current;
• perform an erase operation on the plurality of memory cells, and perform a corresponding erase verification on the plurality of memory cells by adopting the fast bit screening erase verification current;
• perform a soft program operation on the plurality of memory cells, and perform a corresponding soft program verification on the plurality of memory cells by adopting the fast bit screening soft program verification current;
• and
• apply a test voltage to the plurality of word lines coupled to the plurality of memory cells to determine whether the plurality of memory cells are defective memory cells or normal memory cells according to obtained cell currents.