G11C 16/0483
Comprising cells having several storage transistors connected in series
Official title: {comprising cells having several storage transistors connected in series}
G11C16/0483 (Comprising cells having several storage transistors connected in series) appears on 12,288 US grants and 13,926 published applications in this corpus.
Search patents in G11C- Granted patents
- 12,288
- Published applications
- 13,926
- Assignees
- 471
- Inventors
- 7,921
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 3 | 0 |
| 1991 | 4 | 0 |
| 1992 | 3 | 0 |
| 1993 | 8 | 0 |
| 1994 | 13 | 0 |
| 1995 | 11 | 0 |
| 1996 | 21 | 0 |
| 1997 | 22 | 0 |
| 1998 | 28 | 0 |
| 1999 | 37 | 0 |
| 2000 | 55 | 0 |
| 2001 | 42 | 17 |
| 2002 | 39 | 48 |
| 2003 | 50 | 48 |
| 2004 | 44 | 73 |
| 2005 | 76 | 189 |
| 2006 | 118 | 278 |
| 2007 | 204 | 346 |
| 2008 | 250 | 388 |
| 2009 | 323 | 381 |
| 2010 | 328 | 354 |
| 2011 | 360 | 414 |
| 2012 | 365 | 469 |
| 2013 | 436 | 455 |
| 2014 | 565 | 513 |
| 2015 | 565 | 483 |
| 2016 | 616 | 535 |
| 2017 | 558 | 479 |
| 2018 | 491 | 508 |
| 2019 | 651 | 819 |
| 2020 | 873 | 945 |
| 2021 | 895 | 994 |
| 2022 | 903 | 1088 |
| 2023 | 875 | 1172 |
| 2024 | 966 | 1168 |
| 2025 | 901 | 961 |
| 2026 | 588 | 801 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Control gate signal for data retention in nonvolatile memory6 Oct 2026US 12,755,789 B2SanDisk Technologies LLC
- Architecture and method for NAND memory operation6 Oct 2026US 12,755,794 B2Yangtze Memory Technologies Co., Ltd.
- Sense voltage adjustment among multiple erase blocks6 Oct 2026US 12,755,795 B2Micron Technology, Inc.
- Erase method for memory device and memory device6 Oct 2026US 12,755,796 B2Macronix International Co., Ltd.
- Enhanced read retry (ERR) for data recovery in flash memory6 Oct 2026US 12,755,797 B2SanDisk Technologies LLC
- Nonvolatile memory device supporting high-efficiency i/o interface8 Oct 2026US 2026/0310383 A1Samsung Electronics Co., Ltd.
- Fabrication Method for a Memory Structure Including High Density Three-Dimensional NOR Memory Strings of Junctionless Ferroelectric Storage Transistors8 Oct 2026US 2026/0311761 A1Sunrise Memory Corporation
- Memory apparatus8 Oct 2026US 2026/0311762 A1Winbond Electronics Corp.
- Bias voltage control for sub-block groups in a memory device8 Oct 2026US 2026/0311766 A1Micron Technology, Inc.
- Nonvolatile memory device and method of operating the same8 Oct 2026US 2026/0311769 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Multi-state EEPROM having write-verify control circuit972US 5,570,315 AKabushiki Kaisha Toshiba · 1996
- Semiconductor device and memory system940US 6,046,935 AKabushiki Kaisha Toshiba · 2000
- Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states791US 6,522,580 B2SanDisk Corporation · 2003
- Variable programming of non-volatile memory725US 7,020,017 B2SanDisk Corporation · 2006
- Selective operation of a multi-state non-volatile memory system in a binary mode707US 6,456,528 B1SanDisk Corporation · 2002