Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states

A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another, comprising:

• programming data into a first plurality of storage elements,
• thereafter programming data into a second plurality of storage elements,
• thereafter reading data programmed into the first plurality of storage elements, and
• thereafter reprogramming the first plurality of storage elements with the read data, whereby the reprogramming is accomplished without having to retain a copy of the data initially programmed into the first plurality of storage elements.

A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another but where values read from storage elements are affected by values stored by adjacent storage elements because of field coupling between the storage elements, and wherein the individual storage elements are programmed by incrementally changing the storage levels thereof until one of the storage level ranges is reached that corresponds to the data being stored therein, comprising:

• programming data into a plurality of the storage elements by incrementally changing the storage levels of individual storage elements until one of a first set of reference storage levels corresponding to the data being stored is reached or exceeded, thereby to store the data with a distribution of storage levels among the plurality of storage elements within the defined ranges having widths resulting from incrementally changing the storage levels, and
• thereafter reprogramming the storage levels in one portion of individual ones of said distributions into another non-overlapping portion thereof, thereby to reduce the extents of the storage level distributions within the individual defined ranges of storage levels and to increase the separation between the individual defined ranges of storage levels in order to allow for the effects of field coupling between adjacent storage elements.

A method of storing data in a non-volatile array of storage elements individually having a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another, and wherein the individual storage elements are programmed by incrementally changing the storage levels thereof until one of the storage level ranges is reached that corresponds to the data being stored therein, comprising:

• programming data into a first plurality of the storage elements by incrementally changing the storage levels of individual storage elements until one of a first set of reference storage levels corresponding to the data being stored is reached or exceeded, thereby to store the data with distributions of storage levels among the plurality of storage elements within defined ranges having widths resulting from incrementally changing the storage levels,
• thereafter programming data into a second plurality of storage elements,
• thereafter reading data programmed into the first plurality of storage elements, and
• thereafter reprogramming those of the first plurality of storage elements having storage levels in one portion of individual ones of said distributions with the read data by incrementally changing the storage levels of those individual storage elements until programmed into another non-overlapping portion of their respective distributions, whereby the reprogramming is accomplished without having to retain a copy of the data initially programmed into the first plurality of storage elements.

In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures,

• 1) the first program procedure including the steps of:
• a) applying a first program voltage to the memory cell;
• b) generating a first verify flag by determining whether the memory cell has reached a preliminary state;
• and
• c) increasing the first program voltage with a first increasing rate if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,
• 2) the second program procedure determining whether the memory cell has reached the given state,
• 3) the third program procedure, which is exerted on the memory cell if the memory cell has been determined not to have reached the given state, including the steps of:
• d) applying a second program voltage to the memory cell;
• e) generating a second verify flag by determining whether the memory cell has reached the given state;
• and
• f) increasing the second program voltage with a second increasing rate if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures,

• 1) the first program procedure including the steps of:
• a) applying a first program voltage to the memory cell;
• b) generating a fist verify flag by determining whether the memory cell has reached a preliminary state;
• and
• c) increasing the first program voltage with a first increasing rate if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,
• 2) the second program procedure determining whether the memory cell has remained within a specified state not included in the given state,
• 3) the third program procedure, which is exerted on the memory cell if the memory cell has remained within the specified state, including the steps of:
• d) applying a second program voltage to the memory cell;
• e) generating a second verify flag by determining whether the memory cell has reached the given state;
• and
• f) increasing the second program voltage with a second increasing rate if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures,

• 1) the first program procedure including the steps of:
• a) applying a first program voltage to the memory cell;
• b) generating a first verify flag by determining whether the memory cell has reached a preliminary state;
• and
• c) continuing to apply the first program voltage to the memory cell if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,
• 2) the second program procedure determining whether the memory cell has reached the given state,
• 3) the third program procedure, which is exerted on the memory cell if the memory cell has been determined not to have reached the given state, including the steps of:
• d) applying a second program voltage to the memory cell;
• e) generating a second verify flag by determining whether the memory cell has reached the given state;
• and
• f) continuing to apply the second program voltage to the memory cell if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

In a memory array including a memory cell, a method of programming the memory cell to a given state, the method comprising first, second and third program procedures,

• 1) the first program procedure including the steps of:
• a) applying a first program voltage to the memory cell;
• b) generating a first verify flag by determining whether the memory cell has reached a preliminary state;
• and
• c) continuing to apply the first program voltage to the memory cell if the first verify flag indicates that the memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the memory cell,
• 2) the second program procedure determining whether the memory cell has remained within a specified state not included in the given state,
• 3) the third program procedure, which is exerted on the memory cell if the memory cell has remained within the specified state, including the steps of:
• d) applying a second program voltage to the memory cell;
• e) generating a second verify flag by determining whether the memory cell has reached the given state;
• and
• f) continuing to apply the second program voltage to the memory cell if the second verify flag indicates that the memory cell has not reached to the given state, otherwise removing the second program voltage from the memory cell.

In a memory array including first and second memory cells, a method of programming the first and second memory cells to a given state, the second memory cell being programmed after programming the first memory cell, the method comprising first, second, third and fourth program procedures,

• 1) the first program procedure including the steps of:
• a) applying a first program voltage to the first memory cell;
• b) generating a first verify flag by determining whether the first memory cell has reached a preliminary state;
• and
• c) increasing the first program voltage with a first increasing rate if the first verify flag indicates that the first memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the first memory cell,
• 2) the second program procedure determining whether the first memory cell has reached the given state,
• 3) the third program procedure, which is exerted on the first memory cell if the first memory cell has been determined not to have reached the given state, including the steps of:
• d) applying a second program voltage to the first memory cell;
• e) generating a second verify flag by determining whether the first memory cell has reached the given state;
• and
• f) increasing the second program voltage with a second increasing rate if the second verify flag indicates that the first memory cell has not reached to the given state, otherwise removing the second program voltage from the first memory cell,
• 4) the fourth program procedure, which is exerted on the second memory cell after the first, second and third program procedures, including the steps of:
• g) applying a third program voltage to the second memory cell;
• h) generating a third verify flag by determining whether the second memory cell has reached the given state;
• and
• i) increasing the third program voltage with a third increasing rate if the third verify flag indicates that the second memory cell has not reached to the given state, otherwise removing the third program voltage from the second memory cell.

In a memory array including first and second memory cells, a method of programming the first and second memory cells to a given state, the second memory cell being programmed after programming the first memory cell, the method comprising first, second, third and fourth program procedures,

• 1) the first program procedure including the steps of:
• a) applying a first program voltage to the first memory cell;
• b) generating a first verify flag by determining whether the first memory cell has reached a preliminary state;
• and
• c) continuing to apply the first program voltage to the first memory cell if the first verify flag indicates that the first memory cell has not reached to the preliminary state, otherwise removing the first program voltage from the first memory cell,
• 2) the second program procedure determining whether the first memory cell has reached the given state,
• 3) the third program procedure, which is exerted on the first memory cell if the first memory cell has been determined not to have reached the given state, including the steps of:
• d) applying a second program voltage to the first memory cell;
• e) generating a second verify flag by determining whether the first memory cell has reached the given state;
• and
• f) continuing to apply the second program voltage to the first memory cell if the second verify flag indicates that the first memory cell has not reached to the given state, otherwise removing the second program voltage from the first memory cell,
• 4) the fourth program procedure, which is exerted on the second memory cell after the first, second and third program procedures, including the steps of:
• g) applying a third program voltage to the second memory cell;
• h) generating a third verify flag by determining whether the second memory cell has reached the given state;
• and
• i) continuing to apply the third program voltage to the second memory cell if the third verify flag indicates that the second memory cell has not reached to the given state, otherwise removing the third program voltage from the second memory cell.