Erase method for memory device and memory device

A memory device, comprising:

• a memory block, wherein the memory block comprises a plurality of memory cell strings, the plurality of the memory cell strings including a plurality of string selection transistors, a plurality of first-part memory cells, a plurality of dummy cells, a plurality of second-part memory cells, and a plurality of ground selection transistors, wherein each of the plurality of the string selection transistors, each of the plurality of the first-part memory cells, each of the plurality of the dummy cells, each of the plurality of the second-part memory cells, and each of the plurality of the ground selection transistors are connected in series to construct each memory cell string, each of the plurality of the dummy cells are disposed between one of the plurality of the first-part memory cells and one of the plurality of the second-part memory cells, wherein the first-part memory cells on each memory string connected to a plurality of first word lines respectively are constructed as a plurality of first pages, and the second-part memory cells on each memory string connected to a plurality of second word lines are constructed as a plurality of second pages;
• a memory controller, coupled to the memory block to:
• performing a program operation to one of the plurality of the first pages as a selected first page;
• performing the program operation to one of the plurality of the second pages as a selected second page;
• performing a gate induced drain leakage (GIDL) erasing operation to the plurality of the first pages;
• inhibiting the plurality of the second pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the first pages;
• performing the GIDL erasing operation to the plurality of the second pages;
• and
• inhibiting the plurality of the first pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the second pages,
• wherein, after the GIDL operation to the plurality of the first pages and the GIDL operation to the plurality of the second pages, all the first memory cells in a specific memory cell string are the type-1 erase bit or the type-2 erase bit, all the second memory cells in the specific memory cell string are the type-1 erase bit or the type-2 erase bit, and an erase bit type of the first memory cells and an erase bit type of the second memory cells has 0.5 inter-hamming distance.