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US 12,755,794 B2Granted
Architecture and method for NAND memory operation
AssigneeYangtze Memory Technologies Co., Ltd.
InventorKaijin Huang
Life of this patent
Estimating the term…
Abstract
In a method for erasing a memory device including memory cells, a first erase operation is performed on a selected memory cell of the memory cells. A first erase verifying operation is performed on the selected memory cell. A second erase verifying operation is performed on the selected memory cell. A second erase operation is performed on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation.
Claims20
A method of erasing a memory device including memory cells, comprising:
- performing a first erase operation on a selected memory cell of the memory cells;
- performing a first erase verifying operation on the selected memory cell;
- in response to the selected memory cell passing the first erase verifying operation, before performing another erase operation on the selected memory cell, performing a second erase verifying operation on the selected memory cell, wherein the first erase verifying operation and the second erase verifying operation are performed using different erase verify voltages;
- and
- performing a second erase operation on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation.
2 more elements
A memory device, comprising:
- memory cells including a selected memory cell;
- and
- a periphery circuit configured to:
- perform a first erase operation on the selected memory cell;
- perform a first erase verifying operation on the selected memory cell;
- in response to the selected memory cell passing the first erase verifying operation, before performing another erase operation on the selected memory cell, perform a second erase verifying operation on the selected memory cell, wherein the first erase verifying operation and the second erase verifying operation are performed using different erase verify voltages;
- and
- perform a second erase operation on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation.
5 more elements
A system, comprising:
- a memory device including:
- memory cells including a selected memory cell;
- and
- a periphery circuit configured to:
- perform a first erase operation on the selected memory cell;
- perform a first erase verifying operation on the selected memory cell;
- in response to the selected memory cell passing the first erase verifying operation, before performing another erase operation on the selected memory cell, perform a second erase verifying operation on the selected memory cell, wherein the first erase verifying operation and the second erase verifying operation are performed using different erase verify voltages;
- and
- perform a second erase operation on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation;
- and
- a processor coupled to the memory device and configured to send a command to the memory device.
8 more elements
Dependencies are inferred from the claim text.