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US 12,755,795 B2Granted
Sense voltage adjustment among multiple erase blocks
AssigneeMicron Technology, Inc.
InventorsShyam Sunder Raghunathan, Akira Goda, Kishore K. Muchherla
Life of this patent
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Abstract
An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.
Claims16
An apparatus, comprising:
- a memory array comprising a plurality of strings of memory cells, wherein each string of the plurality of strings comprises:
- a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block;
- and
- a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block;
- and
- control circuitry coupled to the memory array and configured to:
- receive a command corresponding to a sensing operation to be performed on a selected access line of the first group of access lines;
- and
- determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation, wherein the adjusted sense voltage is based on:
- a quantity of the first group of access lines that are programmed;
- and
- a quantity of the second group of access lines that are programmed;
- and
- wherein the adjusted sense voltage is further determined based on a first offset factor corresponding to the first erase block and a second offset factor corresponding to the second erase block;
- wherein the first offset factor is multiplied by the quantity of the first group of access lines that are programmed to determine a first offset voltage;
- wherein the second offset factor is multiplied by the quantity of the second group of access lines that are programmed to determine a second offset voltage;
- and
- wherein the adjusted sense voltage is based on an overall sense voltage offset which is a sum of the first offset voltage and the second offset voltage.
15 more elements
A method, comprising:
- tracking, via a controller external to a memory device comprising a plurality of erase blocks, respective erase block program state statuses for the plurality of erase blocks;
- providing, to the memory device:
- a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block or of a second group of access lines corresponding to a second erase block;
- and
- erase block program state information corresponding to the first erase block and erase block program state information corresponding to the second erase block;
- and
- determining, via the memory device, an offset by which a sense voltage to be applied to the selected access line is to be adjusted in association with performing the sensing operation based on the provided erase block program state information corresponding to the first erase block and the provided erase block program state information corresponding to the second block;
- wherein, for a first particular determined quantity of programmed access lines of the first group of access lines and a second particular determined quantity of programmed access lines of the second group of access lines, the offset by which the sense voltage to be applied to the selected access line is adjusted is a first offset voltage or a second offset voltage depending on whether the selected access line is within the first erase block or the second erase block;
- and
- wherein the first offset voltage is different than the second offset voltage.
7 more elements
An apparatus, comprising:
- a memory device comprising a memory array comprising a plurality of erase blocks;
- and
- a controller external to the memory device and configured to:
- track respective erase block program state statuses for the plurality of erase blocks;
- provide, to the memory device:
- a command corresponding to a sensing operation to be performed on a selected access line of the memory array;
- and
- erase block program state information corresponding to a first erase block and erase block program state information corresponding to a second erase block coupled to a same string as the first erase block;
- and
- wherein the memory device is configured to determine an offset by which a sense voltage to be applied to the selected access line is to be adjusted in association with performing the sensing operation based on the provided erase block program state information corresponding to the first erase block and the provided erase block program state information corresponding to the second erase block;
- wherein for a first particular quantity of access lines in the first erase block determined to be programmed and a first particular quantity of access lines in the second erase block determined to be programmed, the offset by which the sense voltage to be applied to the selected access line is to be adjusted in association with performing the sensing operation is determined to be different responsive to the selected access line being within the first erase block than if the selected access line is within the second erase block.
8 more elements
Dependencies are inferred from the claim text.