G06F 9/30043
Load or store instructions
Official title: {LOAD or STORE instructions; Clear instruction}
G06F9/30043 (Load or store instructions) appears on 2,901 US grants and 2,970 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,901
- Published applications
- 2,970
- Assignees
- 473
- Inventors
- 4,330
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 3 | 0 |
| 1983 | 1 | 0 |
| 1984 | 4 | 0 |
| 1985 | 4 | 0 |
| 1986 | 3 | 0 |
| 1987 | 2 | 0 |
| 1988 | 5 | 0 |
| 1989 | 2 | 0 |
| 1990 | 4 | 0 |
| 1991 | 5 | 0 |
| 1992 | 6 | 0 |
| 1993 | 7 | 0 |
| 1994 | 12 | 0 |
| 1995 | 22 | 0 |
| 1996 | 24 | 0 |
| 1997 | 42 | 0 |
| 1998 | 64 | 0 |
| 1999 | 66 | 0 |
| 2000 | 42 | 0 |
| 2001 | 53 | 12 |
| 2002 | 40 | 49 |
| 2003 | 38 | 43 |
| 2004 | 64 | 78 |
| 2005 | 38 | 66 |
| 2006 | 45 | 52 |
| 2007 | 54 | 50 |
| 2008 | 56 | 76 |
| 2009 | 37 | 74 |
| 2010 | 48 | 40 |
| 2011 | 60 | 55 |
| 2012 | 47 | 65 |
| 2013 | 45 | 90 |
| 2014 | 57 | 115 |
| 2015 | 67 | 127 |
| 2016 | 154 | 155 |
| 2017 | 136 | 236 |
| 2018 | 186 | 169 |
| 2019 | 181 | 205 |
| 2020 | 186 | 232 |
| 2021 | 224 | 164 |
| 2022 | 169 | 181 |
| 2023 | 181 | 183 |
| 2024 | 184 | 178 |
| 2025 | 138 | 139 |
| 2026 | 90 | 136 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for persisting hardware transactional memory transactions to persistent memory6 Oct 2026US 12,754,842 B1
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Processor supporting position-independent addressing29 Sep 2026US 12,748,597 B2Oracle International Corporation
- Multi-layer data cache to prevent user experience interrupts during feature flag management15 Sep 2026US 12,737,183 B2Brex Inc.
- Technique for handling ordering constrained access operations15 Sep 2026US 12,737,185 B2Arm Limited
- Control method and chip8 Oct 2026US 2026/0310463 A1Smarter Silicon (Shanghai) Technologies Co., Ltd.
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Apparatus and method for efficient prefetching using secure error correction code (ecc) encoding1 Oct 2026US 2026/0299947 A1
- Vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors1 Oct 2026US 2026/0299952 A1Micron Technology, Inc.
- Combined load value and load address prediction1 Oct 2026US 2026/0299955 A1
Most cited
By later US patents
- Processor-cache system and method417US 9,047,193 B2Shanghai Xin Hao Micro Electronics Co. Ltd. · 2015
- DRAM with high bandwidth interface that uses packets and arbitration313US 5,778,419 AMicroUnity Systems Engineering, Inc. · 1998
- Data processing system with register store/load utilizing data packing/unpacking296US 6,829,696 B1Texas Instruments Incorporated · 2004
- Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register277US 5,758,195 ATexas Instruments Incorporated · 1998
- System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization227US 5,794,062 ARicoh Company, Ltd. · 1998